
6
Evaluation Board
The performance of the HFA1135 may be evaluated using
the HFA11XX evaluation board (part number
HFA11XXEVAL). Please contact your local sales office for
information. When evaluating this amplifier at a gain of +2,
the two 510
gain setting resistors on the evaluation board
should be changed to 250
.
The layout and schematic of the board are shown in Figure 2.
NOTE: The SOIC version may be evaluated in the DIP board by
using a SOIC-to-DIP adapter such as Aries Electronics part number
08-350000-10.
Limiting Operation
General
The HFA1135 features user programmable output clamps to
limit output voltage excursions. Limiting action is obtained by
applying voltages to the V
H
and V
L
terminals (pins 8 and 5)
of the amplifier. V
H
sets the upper output limit, while V
L
sets
the lower limit level. If the amplifier tries to drive the output
above V
H
, or below V
L
, the clamp circuitry limits the output
voltage at V
H
or V
L
(
±
the limit accuracy), respectively. The
low input bias currents of the limit pins allow them to be
driven by simple resistive divider circuits, or active elements
such as amplifiers or DACs.
Limit Circuitry
Figure 3 shows a simplified schematic of the HFA1135 input
stage, and the high limit (V
H
) circuitry. As with all current
feedback amplifiers, there is a unity gain buffer (Q
X1
- Q
X2
)
between the positive and negative inputs. This buffer forces
-IN to track +IN, and sets up a slewing current of:
I
SLEW
= (V
-IN
- V
OUT
)/R
F
+ V
-IN
/R
G
This current is mirrored onto the high impedance node (Z) by
Q
X3
-Q
X4
, where it is converted to a voltage and fed to the
output via another unity gain buffer. If no limiting is utilized,
the high impedance node may swing within the limits defined
by Q
P4
and Q
N4
. Note that when the output reaches its
quiescent value, the current flowing through -IN is reduced to
only that small current (-I
BIAS
) required to keep the output at
the final voltage.
Tracing the path from V
H
to Z illustrates the effect of the limit
voltage on the high impedance node. V
H
decreases by 2V
BE
(Q
N6
and Q
P6
) to set up the base voltage on Q
P5
. Q
P5
begins to conduct whenever the high impedance node
reaches a voltage equal to Q
P5
’s base voltage + 2V
BE
(Q
P5
and Q
N5
). Thus, Q
P5
limits node Z whenever Z reaches V
H
.
R
1
provides a pull-up network to ensure functionality with the
limit inputs floating. A similar description applies to the
symmetrical low limit circuitry controlled by V
L
.
BOARD SCHEMATIC
TOP LAYOUT
BOTTOM LAYOUT
FIGURE 2. EVALUATION BOARD SCHEMATIC AND LAYOUT
1
2
3
4
8
7
6
5
+5V
10
μ
F
0.1
μ
F
V
H
50
GND
GND
510
510
-5V
0.1
μ
F
10
μ
F
50
IN
OUT
V
L
V
H
+IN
V
L
V+
GND
1
V-
OUT
+1
+IN
V-
V+
Q
P1
Q
N1
V-
Q
N3
Q
P3
Q
P4
Q
N2
Q
P2
Q
N4
Q
P5
Q
N5
Z
V+
-IN
V
OUT
I
LIMIT
R
F
(EXTERNAL)
Q
P6
Q
N6
V
H
R
1
V
-IN
200
FIGURE 3. HFA1135 SIMPLIFIED V
H
LIMIT CIRCUITRY
50k
HFA1135