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參數(shù)資料
| 型號： | HEF4046BD |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | XO, clock |
| 英文描述： | Programmable Logic Controller; RoHS Compliant: Yes |
| 中文描述： | PHASE LOCKED LOOP, CDIP16 |
| 文件頁數(shù)： | 3/15頁 |
| 文件大?。?/td> | 416K |
| 代理商： | HEF4046BD |
January 1995
3
Philips Semiconductors
Product specification
Phase-locked loop
HEF4046B
MSI
Fig.2 Pinning diagram.
PINNING
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Source-follower output
11. Resistor R1 connection
12. Resistor R2 connection
13. Phase comparator 2 output
14. Signal input
15. Zener diode input for regulated supply.
Phase comparator pulse output
Phase comparator 1 output
Comparator input
VCO output
Inhibit input
Capacitor C1 connection A
Capacitor C1 connection B
V
SS
VCO input
FUNCTIONAL DESCRIPTION
VCO part
The VCO requires one external capacitor (C1) and one or
two external resistors (R1 or R1 and R2). Resistor R1 and
capacitor C1 determine the frequency range of the VCO.
Resistor R2 enables the VCO to have a frequency off-set
if required. The high input impedance of the VCO simplifies
the design of low-pass filters; it permits the designer a wide
choice of resistor/capacitor ranges. In order not to load the
low-pass filter, a source-follower output of the VCO input
voltage is provided at pin 10. If this pin (SF
OUT
) is used, a
load resistor (R
SF
) should be connected from this pin to
V
SS
; if unused, this pin should be left open. The VCO
output (pin 4) can either be connected directly to the
comparator input (pin 3) or via a frequency divider. A LOW
level at the inhibit input (pin 5) enables the VCO and the
source follower, while a HIGH level turns off both to
minimize stand-by power consumption.
Phase comparators
The phase-comparator signal input (pin 14) can be
direct-coupled, provided the signal swing is between the
standard HE4000B family input logic levels. The signal
must be capacitively coupled to the self-biasing amplifier
at the signal input in case of smaller swings. Phase
comparator 1 is an EXCLUSIVE-OR network. The signal
and comparator input frequencies must have a 50% duty
factor to obtain the maximum lock range. The average
output voltage of the phase comparator is equal to
1
2
V
DD
when there is no signal or noise at the signal input. The
average voltage to the VCO input is supplied by the
low-pass filter connected to the output of phase
comparator 1. This also causes the VCO to oscillate at the
centre frequency (f
o
). The frequency capture range (2 f
c
) is
defined as the frequency range of input signals on which
the PLL will lock if it was initially out of lock. The frequency
lock range (2 f
L
) is defined as the frequency range of input
signals on which the loop will stay locked if it was initially
in lock. The capture range is smaller or equal to the lock
range.
With phase comparator 1, the range of frequencies over
which the PLL can acquire lock (capture range) depends
on the low-pass filter characteristics and this range can be
made as large as the lock range. Phase comparator 1
enables the PLL system to remain in lock in spite of high
amounts of noise in the input signal. A typical behaviour of
this type of phase comparator is that it may lock onto input
frequencies that are close to harmonics of the VCO centre
frequency. Another typical behaviour is, that the phase
angle between the signal and comparator input varies
between 0
°
and 180
°
and is 90
°
at the centre frequency.
Figure 3 shows the typical phase-to-output response
characteristic.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HEF4046BF | Phase-locked loop |
| HEF4046BN | Programmable Logic Controller; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No RoHS Compliant: No |
| HEF4052B | Dual 4-channel analogue multiplexer/demultiplexer(雙四通道模擬多路復(fù)用器/多路分解器) |
| HEF4059B | Programmable divide-by-n counter(可編程÷n計數(shù)器) |
| HEF4060B | 14-stage ripple-carry binary counter/divider and oscillator(14級紋波進位二進制計數(shù)器/除法器和振蕩器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HEF4046BF | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Phase-locked loop |
| HEF4046BN | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Phase-locked loop |
| HEF4046BP | 制造商:NXP Semiconductors 功能描述:IC 4000 LOCMOS LOGIC 制造商:NXP Semiconductors 功能描述:IC, 4000 LOCMOS LOGIC 制造商:NXP 功能描述:2.7Mhz 16-DIP Phase Lock Loop 制造商:NXP Semiconductors 功能描述:IC, PHASE LOCK LOOP, 2.7MHZ, 16-DIP; PLL Type:VCO; Frequency:7MHz; Supply Current:750A; Supply Voltage Min:3V; Supply Voltage Max:15V; Digital IC Case Style:DIP; No. of Pins:16; Operating Temperature Min:-40C; Family Type:4000 CMOS;RoHS Compliant: Yes |
| HEF4046BP,652 | 功能描述:鎖相環(huán) - PLL PHASE LOCKED LOOP W/VCO RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| HEF4046BP652 | 制造商:NXP Semiconductors 功能描述:IC PHASE LOCKED LOOP (PLL) VCO 2.7MHZ |
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