參數(shù)資料
型號: HEF4015BP
廠商: NXP Semiconductors N.V.
元件分類: 通用總線功能
英文描述: Dual 4-bit static shift register
封裝: HEF4015BP<SOT38-4 (DIP16)|<<http://www.nxp.com/packages/SOT38-4.html<1<Always Pb-free,;HEF4015BT<SOT109-1 (SO16)|<<http://www.nxp.com/packages/SOT109-1.html<1<week
文件頁數(shù): 7/15頁
文件大?。?/td> 144K
代理商: HEF4015BP
HEF4015B
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 14 September 2011
7 of 15
NXP Semiconductors
HEF4015B
Dual 4-bit static shift register
12. Waveforms
Table 8.
P
D
can be calculated from the formulas shown. V
SS
= 0 V; t
r
= t
f
20 ns; T
amb
= 25
C.
Symbol
Parameter
V
DD
Typical formula for P
D
(
W)
P
D
dynamic power
dissipation
10 V
P
D
= 6300
f
i
+
(f
o
C
L
)
V
DD2
15 V
P
D
= 17000
f
i
+
(f
o
C
L
)
V
DD2
Dynamic power dissipation P
D
where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
DD
= supply voltage in V;
(C
L
f
o
) = sum of the outputs.
5 V
P
D
= 1500
f
i
+
(f
o
C
L
)
V
DD2
Measurement points are given in
Table 9
.
Fig 4.
Waveforms showing nCP propagation delays and nQn transition times
001aaj464
t
PHL
t
t
t
t
nCP input
nQn output
V
I
V
SS
V
M
V
OH
V
OL
V
M
10 %
90 %
t
PLH
The shaded area indicates where the input is permitted to change for predictable output performance.
Set-up and hold times are shown as positive values but may be specified as negative values;
Measurement points are given in
Table 9
.
Fig 5.
Waveforms showing set-up times, hold times, and minimum clock pulse width
nCP input
nD input
001aae563
t
W
t
h
V
M
V
M
V
M
V
M
t
su
t
su
t
h
1/f
max
V
M
V
M
V
I
V
M
V
SS
V
I
V
SS
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