參數(shù)資料
型號: HEF4015BP
廠商: NXP Semiconductors N.V.
元件分類: 通用總線功能
英文描述: Dual 4-bit static shift register
封裝: HEF4015BP<SOT38-4 (DIP16)|<<http://www.nxp.com/packages/SOT38-4.html<1<Always Pb-free,;HEF4015BT<SOT109-1 (SO16)|<<http://www.nxp.com/packages/SOT109-1.html<1<week
文件頁數(shù): 1/15頁
文件大小: 144K
代理商: HEF4015BP
1. General description
The HEF4015B is a dual edge-triggered 4-bit static shift register (serial-to-parallel
converter). Each shift register has a serial data input (D), a clock input (CP), four fully
buffered parallel outputs (Q0 to Q3) and an overriding asynchronous master reset input
(MR). Information present on D is shifted to the first register position, and all the data in
the register is shifted one position to the right on the LOW-to-HIGH transition of CP. A
HIGH on MR clears the register and forces Q0 to Q3 to LOW, independent of CP and D.
The clock input’s Schmitt trigger action makes the input highly tolerant of slower clock rise
and fall times.
It operates over a recommended V
DD
power supply range of 3 V to 15 V referenced to V
SS
(usually ground). Unused inputs must be connected to V
DD
, V
SS
, or another input. It is
also suitable for use over the full industrial (
40
C to +85
C) temperature range.
2. Features and benefits
Tolerant of slow clock rise and fall times
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Operates across the automotive temperature range
40
C to +85
C.
Complies with JEDEC standard JESD 13-B
3. Applications
Serial-to-parallel converter
Buffer stores
General purpose register
4. Ordering information
HEF4015B
Dual 4-bit static shift register
Rev. 7 — 14 September 2011
Product data sheet
Table 1.
All types operate from
40
C to +85
C.
Type number
Package
Name
HEF4015BP
DIP16
HEF4015BT
SO16
Ordering information
Description
plastic dual in-line package; 16 leads (300 mil)
plastic small outline package; 16 leads; body width 3.9 mm
Version
SOT38-4
SOT109-1
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