參數(shù)資料
型號: HEF4014BP
廠商: NXP Semiconductors N.V.
元件分類: 通用總線功能
英文描述: 8-bit static shift register
封裝: HEF4014BP<SOT38-4 (DIP16)|<<http://www.nxp.com/packages/SOT38-4.html<1<Always Pb-free,;HEF4014BT<SOT109-1 (SO16)|<<http://www.nxp.com/packages/SOT109-1.html<1<week
文件頁數(shù): 4/14頁
文件大小: 143K
代理商: HEF4014BP
HEF4014B
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 14 September 2011
4 of 14
NXP Semiconductors
HEF4014B
8-bit static shift register
7. Functional description
[1]
H = HIGH voltage level; L = LOW voltage level; X = don’t care; nD = HIGH or LOW;
= LOW-to-HIGH clock transition;
= HIGH-to-LOW clock transition;
8. Limiting values
[1]
For DIP16 package: P
tot
derates linearly with 12 mW/K above 70
C.
For SO16 package: P
tot
derates linearly with 8 mW/K above 70
C.
[2]
Table 3.
Number of clock
transitions
Function table
[1]
Inputs
CP
Outputs
Q5
DS
PE
Q6
Q7
Serial operation
1
2
3
6
7
8
1D
2D
3D
X
X
X
X
L
L
L
L
L
L
X
X
X
X
1D
2D
3D
no change
X
X
X
X
1D
2D
no change
X
X
X
X
X
1D
no change
Parallel operation
1
X
X
H
X
D5
no change
D6
no change
D7
no change
Table 4.
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
V
DD
supply voltage
I
IK
input clamping current
V
I
input voltage
I
OK
output clamping current
I
I/O
input/output current
I
DD
supply current
T
stg
storage temperature
T
amb
ambient temperature
P
tot
total power dissipation
Limiting values
Conditions
Min
0.5
-
0.5
-
-
-
65
40
Max
+18
10
V
DD
+ 0.5
10
10
50
+150
+85
Unit
V
mA
V
mA
mA
mA
C
C
V
I
<
0.5 V or V
I
> V
DD
+ 0.5 V
V
O
<
0.5 V or V
O
> V
DD
+ 0.5 V
T
amb
=
40
C to +85
C
DIP16 package
SO16 package
per output
[1]
-
750
500
100
mW
mW
mW
[2]
-
P
power dissipation
-
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