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King Billion Electronics Co., Ltd
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億
電
子
股
份
有
限
公
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HE85750
HE80000 SERIES
6.1.
LCDC Control register
2003/7/30
This specification is subject to change without notice. Please contact sales person for the latest version before use.
8
V1.52E
The contrast of LCD panel can be adjusted by GRAY bits of LCDC register.
LCDC
bit 7
bit 6
Field
GRAY (Contrast adjustment)
Reset
-
-
Field
Value
Function
000000 LCD is darkest
GRAY
111111 LCD is lightest
0
Normal display
BLANK
1
LCD display blanked. LCD driver changes only COM output signal, SEG
signal remains unchanged.
0
LCD driver disabled, LCD driver has no output signal.
LCDE
1
LCD driver Enabled
bit 5
bit 4
bit 3
bit 2
bit 1
BLANK LCDE
0
bit 0
-
-
-
-
0
Please note that LCD driver must be turned off before the entering sleep mode. That means user must
clear the bit 0 of LCDC to turn off LCD driving circuit before setting bit6 of OP1 to enter sleep mode.
Large current might happen if the procedure is not followed.
Please also note that LCD driver uses slow clock as clock source. The LCD display will not display
normally if it works in Fast clock only mode because the LCD refresh action is too fast.
There are two LCD driver configurations.
MO_LCDBS LCD Bias R
≈
000
001
010
011
100
101
110
111
30K ohm
60K ohm
90K ohm
120K ohm
210K ohm
240K ohm
270K ohm
300K ohm