
King Billion Electronics Co., Ltd
駿
億
電
子
股
份
有
限
公
司
HE85750
HE80000 SERIES
2003/7/30
This specification is subject to change without notice. Please contact sales person for the latest version before use.
13
V1.52E
T1H
T1L
< Timer1 Counter >
Decreases 1
Count To
0xFFFFh
The contents of
T1H and T1L are
almost loaded into
Timer1 immediately
when Timer1 is
enabled after reset.
Auto reload
when Timer1
is underflow
Yes
No
Timer1
Interrupt
Request
T1_INT
The Timer1 related control registers are list as below:
Register Address
Field
Bit position Mode
Description
IER
0x02
TC1_IER
2
R/W
0: TC1 interrupt is disabled. (default)
1: TC1 interrupt is enabled.
Low byte of TC1 pre-load value
High byte of TC1 pre-load value
0: TC1 is disabled. (default)
1: TC1 is enabled.
T1L
T1H
0x03
0x04
T1L[7:0]
T1H[7:0]
7~0
7~0
W
W
OP1
0x09
TC1E
2
R/W
11.
Timer2
Timer2 is similar in structure to Timer1 except that clock source of Timer2 comes from the system clock
“Fsys”/1.5. The system clock “Fsys” varies depending on the operation modes of the MCU.
The Timer2 consists of two 8-bit write-only preload registers T2H and T2L and 16-bit down counter. If
Timer2 is enabled, counter will decrement by one with each incoming clock pulse. Timer2 interrupt will
be generated when the counter underflows - counts down to FFFFH. And it will be automatically reloaded
with the value of T2H and T2L.
Please note that the interrupt signal is generated when counter counts from 0000H to FFFFH. If the value
of counter is N, and count down to FFFFH, the total count is N+1. The content of counter is zero when
system resets. Once it is enabled to count at this time, the interrupt will be generated immediately and
value of T2H and T2L will be loaded since the counter counts to FFFFH. So the T2H and T2L value
should be set before enabling Timer2.