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參數(shù)資料
| 型號： | HE84G770B |
| 廠商： | King Billion Electronics Co., Ltd. |
| 英文描述： | 8-BIT MICRO-CONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 5/61頁 |
| 文件大?。?/td> | 817K |
| 代理商： | HE84G770B |
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King Billion Electronics Co., Ltd
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HE84G770
HE80004H SERIES
October 31, 2003
This specification is subject to change without notice. Please contact sales person for the latest version before use.
5
Version:V1.1
Pin Name
LCAP1A
LVL5
LVL4
LVL3
LVL2
LVL1
LGS1
I/O
O Charge Pump Capacitor Pin.
P LCD Bias Voltage 5.
P LCD Bias Voltage 4
P
LCD Bias Voltage 3
P LCD Bias Voltage 2
P LCD Bias Voltage 1.
I Regulator Voltage Setting
O Voltage Regulator Output. VDD is regulated to generate LVREG, which is in turns pumped
to LVL5. Adjust resistor between LGS1 and LVREG to set LVREG voltage.
I Charge Pump Input. The buffered output of the fine-adjusted VREG.
P Power Ground Input.
O DAC Output.
O Alternate output of DAC.
I Inverting input of OP Amp.
I Non-inverting input of OP Amp.
O Output of OP Amp.
I System Reset Input Pin. Level trigger, active low on this pin will put the chip in reset state.
External fast clock pin. Two types of oscillator can be selected by MO_FXTAL (‘0’ for RC
type and ‘1’ for crystal type). For RC type oscillator, one resistor needs to be connected
between FXI and GND. For crystal oscillator, one crystal needs to be placed between FXI
and FXO. Please refer to application for details.
I Test input pin. Please bond this pad and reserve a test point on PCB for debugging. But for
improving ESD, please connect this point with zero Ohm resistor to GND
.
External slow clock pins. Slow clock is clock source for LCD display, TIMER1, Time-Base
and other internal blocks. Both crystal and RC oscillator are provided. The slow clock type
can be selected by mask option MO_SXTAL. Choose ‘0’ for RC type and ‘1’ for crystal
oscillator.
I Input pin for x32 PLL circuit. Connect to external resistor and capacitors as shown in
application circuit.
O
LCD frame signal for interfacing with LCD segment extender KDGS80.
O
LCD data load pin for interfacing with LCD segment extender KDGS80.
P Positive power Input. A 0.1 μF decoupling capacitors should be placed as close to IC VDD
and GND pads as possible for best decoupling effect.
8-bit bi-directional I/O port D. The output type of I/O pad can also be selected by mask
option MO_DPP[7..0] (‘1’ for push-pull and ‘0’ for open-drain).
As the output structure of I/O pad does not contain tri-state buffer. When using the I/O as
input, ‘1’ must be outputted before reading the pin.
PRTD[7..2] can be used as wake-up pins. PRTD[7..6] can be as external interrupt sources.
PRTD[1] shares pad with UART Receiver SIN pin.
PRTD[0] shares pad with UART transmitter SOUT pin.
O Dedicated Ground for PWM output.
O The PWM output can drive speaker or buzzer directly. Set the bit2 of VOC register as one to
turn on PWM. Using VDD & PWM to drive output device.
O The Infrared output.
4-bit bi-directional I/O port C. The output type of I/O pad can also be selected by mask
option MO_CPP[7..4] (‘1’ for push-pull and ‘0’ for open-drain).
As the output structure of I/O pad does not contain tri-state buffer. When using the I/O as
input, ‘1’ must be outputted before reading the pin.
PRTC[7..4] is shared with Key Scan Dedicated Input SCNI[3..0]. The Key Scan function
can be disabled by clearing MO_LCDKEY mask option to ‘0’.
P Dedicated power input for RAM
O COM[32..79] pads are shared with SEG[127..80] outputs. The functions of the pads to be
Description
LVREG
VR12
GND
VO
DAO
OPIN
OPIP
OPO
RSTP_N
FXO,
FXI
O,
B
TSTP_P
SXO,
SXI
O,
I
VX
OLFR
OCCK
VDD
PRTD[7..2]
PRTD[1]/SIN
PRTD[0]/SOUT
B
GND_PWM
PWM
IRO
PRTC[7..4]/
SCNI[3..0]
B
VDD_RAM
CMSG[32..79]
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