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參數(shù)資料
| 型號： | HDMP-T1636A |
| 英文描述： | Gigabit Ethernet Serialize/Deserialize (SerDes) IC(千兆位以太網(wǎng)串行器/解串行器) |
| 中文描述： | 千兆以太網(wǎng)序列化/反序列化器（SerDes）集成電路（千兆位以太網(wǎng)串行器/解串行器） |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 248K |
| 代理商： | HDMP-T1636A |
6
HDMP-1636A/46A/T1636A (Receiver Section)
Timing Characteristics
T
A
= 0
°
C to +70
°
C, V
CC
= 3.15 V to 3.45 V
Symbol
b_sync
[1,2]
Bit Sync Time
f_lock
Frequency Lock at Powerup
t
valid_before
Time Data Valid Before Rising Edge of RBC
t
valid_after
Time Data Valid After Rising Edge of RBC
t
duty
RBC Duty Cycle
t
A-B[3]
Rising Edge Time Difference between
RBC0 and RBC1
t_rxlat
[4]
Receiver Latency
Parameter
Units
bits
μ
s
nsec
nsec
%
nsec
Min.
Typ.
Max.
2500
500
2.5
1.5
40
7.5
60
8.5
nsec
bits
22.4
28.0
Notes:
1. This is the recovery time for input phase jumps, per the Fibre Channel Specification X3.230-1994 FC-PH Standard, Sec 5.3.
2. Tested using C
PLL
= 0.1
μ
F.
3. Garranteed at room temperature.
4. The receiver latency, as shown in Figure 6, is defined as the time between receiving the first serial bit of a parallel data word
(defined as the first edge of the first serial bit) and the clocking out of that parallel word (defined by the rising edge of the receive
byte clock, either RBC1 or RBC0).
DATA BYTE A
DATA BYTE D
RX[0]-RX[9]
DATA BYTE D
± DIN
1.4 V
t_rxlat
R5
R6
R7
R8
R9
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R2
R3
R4
R5
RBC1/0
DATA BYTE C
DATA
DATA
RX[0]-RX[9]
t
valid_before
t
valid_after
RBC1
K28.5
DATA
DATA
1.4 V
2.0 V
0.8 V
2.0 V
BYTSYNC
RBC0
t
A-B
0.8 V
1.4 V
Figure 6. Receiver Latency.
Figure 5. Receiver Section Timing.
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