參數(shù)資料
型號(hào)： HDMP-1636
英文描述： Software
中文描述： 千兆以太網(wǎng)收發(fā)器芯片
文件頁數(shù)： 6/15頁
文件大小： 325K
代理商： HDMP-1636
716
HDMP-1636/46 (Receiver Section)
Timing Characteristics
T
A
= 0
°
C to +70
°
C, V
CC
= 3.15 V to 3.45 V
Symbol
b_sync
[1,2]
Bit Sync Time
t
valid_before
Time Data Valid Before Rising Edge of RBC
t
valid_after
Time Data Valid After Rising Edge of RBC
t
duty
RBC Duty Cycle
t
A-B
Rising Edge Time Difference
t_rxlat
[3]
Receiver Latency
Parameter
Units
bits
nsec
nsec
%
nsec
nsec
bits
Min.
Typ.
Max.
2500
2.5
1.5
40
7.5
TBD
TBD
60
8.5
7.9
22.4
28
Notes:
1. This is the recovery time for input phase jumps, per the Fibre Channel Specification X3.230-1994 FC-PH Standard, Sec 5.3.
2. Tested using C
PLL
= 0.1
μ
F.
3. The receiver latency, as shown in Figure 6, is defined as the time between receiving the first serial bit of a parallel data word
(defined as the first edge of the first serial) and the clocking out of that parallel word (defined by the rising edge of the receive byte
clock, either RBC1 or RBC0).
DATA
DATA
RX[0]-RX[9]
t
valid_before
t
valid_after
RBC1
K28.5
DATA
DATA
1.4 V
2.0 V
0.8 V
2.0 V
BYTSYNC
RBC0
t
A-B
0.8 V
1.4 V
Figure 6. Receiver Latency.
Figure 5. Receiver Section Timing.
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