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參數(shù)資料
| 型號(hào)： | HDMP-1536 |
| 英文描述： | Fibre Channel Transceiver Chip |
| 中文描述： | 光纖通道收發(fā)器芯片 |
| 文件頁(yè)數(shù)： | 12/15頁(yè) |
| 文件大小： | 259K |
| 代理商： | HDMP-1536 |
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707
TRx I/O Definition
Name
BYTSYNC
Pin
47
Type
O-TTL
Signal
Byte Sync Output:
An active high output. Used to indicate detection of
either a comma character or a K28.5 special character (0011111XXX). It
is only active when ENBYTSYNC is enabled.
Serial Data Inputs:
High-speed inputs. Serial data is accepted from the
±
DIN inputs when LOOPEN is low.
HS_OUT
Serial Data Outputs:
High-speed outputs. These lines are active when
LOOPEN is set low. When LOOPEN is set high, these outputs are held
static.
I-TTL
Enable Byte Sync Input:
When high, turns on the internal byte sync
function to allow clock synchronization to a comma character, or a
K28.5 character (0011111XXX). When the line is low, the function is dis-
abled and will not reset registers and clocks, or strobe the BYTSYNC line.
S
Logic Ground:
Normally 0 volts. This ground is used for internal PECL
logic. It should be isolated from the noisy TTL ground as well as possible.
-DIN
+DIN
-DOUT
+DOUT
52
54
61
62
HS_IN
ENBYTSYNC
24
GND
21
25
58
51
GND_RXA
S
Analog Ground:
Normally 0 volts. Used to provide a clean ground
plane for the receiver PLL and high-speed analog cells.
Ground:
Normally 0 volts.
TTL Receiver Ground:
Normally 0 volts. Used for the TTL output cells
of the receiver section.
GND_RXHS
GND_RXTTL
56
32
33
46
15
S
S
GND_TXA
S
Analog Ground:
Normally 0 volts. Used to provide a clean ground plane
for the PLL and high-speed analog cells.
Ground:
Normally 0 volts.
TTL Transmitter Ground:
Normally 0 volts. Used for the TTL input cells
of the transmitter section.
Lock to Reference:
When low, causes the PLL to acquire frequency and
phase lock on the external reference, supplied at REFCLK. When high,
the Rx PLL will automatically frequency lock to REFCLK and phase lock
to the high speed data stream.
Loopback Enable Input:
When set high, the high-speed serial signal is
internally wrapped from the transmitter’s serial loopback outputs back
to the receiver’s loopback inputs. Also, when in loopback mode, the
±
DOUT outputs are held static. When set low,
±
DOUT outputs and
±
DIN inputs are active.
Receiver Byte Clocks:
The receiver section recovers two 53.125 MHz
receive byte clocks. These two clocks are 180 degrees out of phase.
The receiver parallel data outputs are alternatively clocked on the
rising edge of these clocks. The rising edge of RBC1 aligns with the
output of the comma character (for byte alignment) when detected.
Reference Clock and Transmit Byte Clock:
A 106.25 MHz clock
supplied by the host system. The transmitter section accepts this signal
as the frequency reference clock. It is multiplied by 10 to generate the
serial bit clock and other internal clocks. The transmit side also uses this
clock as the transmit byte clock for the incoming parallel data
TX[0]..TX[9]. It also serves as the reference clock for the receive
portion of the transceiver.
GND_TXHS
GND_TXTTL
64
1
14
27
S
S
-LCKREF
I-TTL
LOOPEN
19
I-TTL
RBC1
RBC0
30
31
O-TTL
REFCLK
22
I-TTL
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HDMP-1546 | Fibre Channel Transceiver Chip |
| HDMP-1546A | Fibre Channel Transceiver Chip(光纖通道收發(fā)器芯片) |
| HDMP-1536A | Fibre Channel Transceiver Chip(光纖通道收發(fā)器芯片) |
| HDMP-1636 | Software |
| HDMP-1646 | Gigabit Ethernet Transceiver Chip |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HDMP-1536A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fiber-Optic Transceiver |
| HDMP-1546 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transceiver Chip |
| HDMP-1546A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:IC-TRANSCEIVER |
| HDMP-1636 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Gigabit Ethernet Transceiver Chip |
| HDMP-1636A | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Gigabit Ethernet and Fibre Channel SerDes ICs |
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