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參數(shù)資料
| 型號(hào)： | HDD64M72D18W-13A |
| 廠商： | Hanbit Electronics Co.,Ltd. |
| 英文描述： | DDR SDRAM Module 512Mbyte (64Mx72bit), based on 32Mx8, 4Banks, 8K Ref., with 184Pin-DIMM |
| 中文描述： | DDR SDRAM內(nèi)存模塊512Mbyte（64Mx72bit），在32Mx8，4Banks，8K的參考依據(jù)。與184Pin - DIMM內(nèi)存 |
| 文件頁(yè)數(shù)： | 7/12頁(yè) |
| 文件大?。?/td> | 190K |
| 代理商： | HDD64M72D18W-13A |
HANBit
HDD64M72D18W
URL : www.hbe.co.kr 7 HANBit Electronics Co.,Ltd
.
REV 1.0 (August.2002)
Active standby
current
I
DD3N
CS# >= VIH(min), CKE>=VIH(min)
one
bank
active,
tRC=tRASmax
tCK = 100Mhz for DDR200, 133Mhz for DDR266A
& DDR266B, DQ, DQS and DM inputs changing
twice per clock cycle Address and other control
inputs changing once per clock cycle
active
–
precharge,
1053
900
900
mA
Operating current
(burst read)
I
DD4R
BL = 2, reads, continuous burst
One bank open, Address and control inputs
changing once per clock cycle, I
OUT
= 0mA
1620
1845
1845
mA
Operating current
(Bust write)
I
DD4W
BL = 2, write, continuous burst
One bank open, Address and control inputs
changing once per clock cycle
1485
1755
1755
mA
Auto refresh current
I
DD5
tRC = tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz,
distributed refresh
1845
2070
2070
mA
Normal
54
54
54
Self
refresh
current
Low Power
I
DD6
CKE =< 0.2V, External clock should be on
tCK = 100Mhz for DDR200, 133Mhz for DDR266A
& DDR266B
27
27
27
mA
Operating current
(Four bank operation)
I
DD7A
Four bank interleaving with BL=4
-Refer to the following page for detailed test
condition
2790
3015
3015
mA
Notes:
Operation at above absolute maximum rating can adversely affect device reliability
AC OPERATING CONDITIONS
PARAMETER
STMBOL
MIN
MAX
UNIT
NOTE
Input High (Logic 1) Voltage, DQ, DQS and DM signals
V
IH
(AC)
VREF + 0.31
3
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
V
IL
(AC)
VREF - 0.31
V
3
Input Differential Voltage, CK and CK inputs
V
ID
(AC)
0.7
VDDQ+0.6
V
1
Input Crossing Point Voltage, CK and CK inputs
Notes:
1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of V
IX
is expected to equal 0.5* V
DDQ
of the transmitting device and must track variations in the DC level of
the same
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the
pad in simula-tion. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited
20MHz.
AC OPERATING TEST CONDITIONS
V
IX
(AC)
0.5*VDDQ-0.2
0.5*VDDQ+0.2
V
2
PARAMETER
VALUE
UNIT
NOTE
Input reference voltage for Clock
0.5 * V
DDQ
V
Input signal maximum peak swing
1.5
V
Input signal minimum slew rate
1.0
V
Input Levels(V
IH
/V
IL
)
V
REF
+0.35/V
REF
V
Input timing measurement reference level
V
REF
V
Output timing measurement reference level
V
TT
V
Output load condition
See Load Circuit
V
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