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參數資料
| 型號： | HD74SSTV16859 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 1:2 13-bit SSTL_2 Registered Buffer(1:2 13-位 SSTL_2 寄存緩沖器) |
| 中文描述： | 1:2 13位SSTL_2注冊緩沖區(qū)（1:2 13 -位SSTL_2寄存緩沖器） |
| 文件頁數： | 8/15頁 |
| 文件大小： | 68K |
| 代理商： | HD74SSTV16859 |
HD74SSTV16859
8
Switching Characteristics
Item
Symbol
V
CC
= 2.5
±
0.2 V
Min
Unit
Test Condition
Max
Clock frequency
*1
f
clock
t
su
—
200
MHz
Setup time
Fast slew rate
*4, 6
0.75
—
ns
Data before CLK
↑
,
CLK
↓
Slow slew rate
*5, 6
0.9
—
Hold time
Fast slew rate
*4, 6
t
h
0.75
—
ns
Data after CLK
↑
,
CLK
↓
Slow slew rate
*5, 6
0.9
—
Differential inputs
active time
t
act
22
—
ns
Data inputs must be low
after
RESET
high.
Differential inputs
inactive time
t
inact
22
—
ns
Data and clock inputs
must be held at valid
levels (not floating) after
RESET
low.
CLK
,
CLK
“H” or “L”
Pulse width
t
w
t
SL
2.5
—
ns
Output slew
*3
1
4
volt/ns
(C
L
= 30 pF, R
L
= 50
, V
REF
= V
TT
= V
DDQ
×
0.5)
Item
Symbol
V
CC
= 2.5
±
0.2 V
Min
Unit
FROM
TO
Typ
Max
(Input)
(Output)
Maximum clock frequency
f
max
t
PLH,
t
PHL
t
PHL
200
—
—
MHz
Propagation delay time
*2
1.1
—
2.8
ns
CLK,
CLK
QA, QB
RESET
—
—
5.0
QA, QB
Notes: 1. Although the clock is differential, all timing is relative to CLK going high and
CLK
going low.
2. This timing relationship is specified into test load (see waveforms – 3, 4) with all of the outputs
switching.
3. Assumes into an equivalent, distributed load to the address net structure defined in the
application information provided in this specification.
4. For data signal input slew rate
≥
1 V/ns.
5. For data signal input slew rate
≥
0.5 V/ns and < 1 V/ns.
6. CLK,
CLK
signals input slew rates are
≥
1 V/ns.
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