參數(shù)資料
型號: HD66702R
廠商: Hitachi,Ltd.
英文描述: Low-Power Dot-Matrix Liquid Crystal Display Controller/Driver with Key Scan Function
中文描述: 低功耗點陣液晶顯示控制器/鍵掃描功能驅(qū)動程序
文件頁數(shù): 48/97頁
文件大?。?/td> 513K
代理商: HD66702R
HD66727
48
a) Basic Data-Receive Timing through the I2C Bus Interface
1st byte
Instructions
Transfer end
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
D7 D6 D5 D4
0
0
1
1 1
0
1
1 1
2nd instruction
Device ID code
Slave address
1st instruction
SCL
(Input)
SDA
(Input/
output)
ID0
ID1
ID0
ID1
RS
D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Transfer start
MSB
25 26
Ack
Ack
Ack
27
Acknowledge
RS
MSB
R/
W
b) Basic Data-Transmit Timing through the I2C Bus Interface
1st byte
Instructions
Transfer end
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
D7 D6 D5 D4
1
2nd read
Device ID code
Slave address
1st read
SCL
(Input)
SDA
(Input/
output)
RS
D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Transfer start
MSB
25 26
Ack
Ack
Ack
27
RS
MSB
R/
W
1st byte
SCL
(Input)
SDA
(Input/
output)
d) Consecutive Key-Scanned Data-Transmit Timing through the I2C Bus Interface
1 2 3 4 5 6 7 8 9 101112 131415 161718 19
S
Key-scanned data
(SCAN0)
A
C
K
A
C
K
A
C
K
2021 222324 252627 282930 313233 343536
A
C
K
P
Start
End
1st byte
RAM data 1
execution time
SCL
(Input)
SDA
(Input/
output)
e) Consecutive RAM Data-Transmit Timing through the I2C Bus Interface
1 2 3 4 5 6 7 8 9 101112 131415 161718 19
S
RAM data 1
A
C
K
A
C
K
A
C
K
2021 222324 252627 282930 313233 343536
RAM data 2
execution time
A
C
K
P
Start
End
Transfers the RAM data-2 ACK after the RAM data 1 has been executed.
RAM data 2
RAM data 3
Key-scanned data
(SCAN1)
Key-scanned data
(SCAN2)
Transfers the ACK after 8-bit data has been transmitted.
1st byte
Instruction 1
execution time
SCL
(Input)
SDA
(Input/
output)
S
1 2 3 4 5 6 7 8 9 101112 131415 161718 19
Instruction 1
A
C
K
A
C
K
Instruction 2
A
C
K
2021 222324 252627 282930 313233 343536
Instruction 2
execution time
Instruction 3
A
C
K
P
Start
End
Transfers the instruction-2 ACK after instruction 1 has been executed.
c) Consecutive Instruction-Receive Timing through the I2C Bus Interface
Acknowledge
Acknowledge
Acknowledge
Acknowledge
Acknowledge
Figure 23 I
2
C Bus Interface Timing Sequence
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