參數(shù)資料
型號: HD66522
廠商: Hitachi,Ltd.
英文描述: 160-Channel Column Driver with Internal Bit-Map RAM for Reflective Color Display and Grayscale Display(點陣圖形LCD160通道驅(qū)動器)
中文描述: 160通道,內(nèi)置欄位為反射式彩色顯示和灰度顯示屏(點陣圖形LCD160通道驅(qū)動器地圖RAM驅(qū)動器)
文件頁數(shù): 16/47頁
文件大小: 276K
代理商: HD66522
HD66522
16
It is recommended that the grayscale palletes are written while
DISPOFF
is low. If HD66523R’s
DOC
signal is connected to
DISPOFF
,
DISPOFF
signal will be low for four frame period after reset.
Address Management
The HD66522 has an address management function that corresponds to four display sizes all of which are
standard sizes for portable information devices: a 160-dot-wide by 240-dot-long display (small information
devices); a 320-dot-wide by 240-dot-long display (quarter VGA size); a 320-dot-wide by 480-dot-long
display (half VGA size); and a 640-dot-wide by 480-dot-long display (VGA size). Up to eight HD66522s
can be connected to at a time to configure easily liquid crystal displays with the resolutions mentioned
above.
Driver Layout and Address Management
The Y lines on a liquid crystal panel and memory data in a driver are inverted horizontally depending on
the connection side of the liquid crystal panel and the driver. When several drivers are connected, address
management is needed for each driver. Although reinverted bit-map plotting or address management by the
C S
pin in each driver are possible by using special write addressing, the load on the software is
significantly increased. To avoid this, the HD66522 provides memory addresses independent of connection
side, but responds to the setting of pins LS0, LS1, LS2 and SHL.
How to Use the LS2, LS1 and LS0 Pins
Pins LS2, LS1 and LS0 set the position (up to eight) as shown in Figure 7 by assigning ID numbers 0 to 7
to each HD66522.
HD66522 HD66522
HD66522 HD66522
ID=1
H
H
ID=0
ID=2
ID=3
HD66522 HD66522
HD66522
ID=5
HD66522
ID=7
ID=4
ID=6
480
LCD panel
L: Low Level H: High Level
LS2 LS1 LS0 ID No. RAM Address Arrangement
L
L
L
0
L
H
L
2
H
L
L
4
H
H
L
6
Upper-side
Left to Right
L
L
H
H
L
H
L
H
H
H
H
H
1
3
5
7
Lower-side
Left to Right
640
Figure 7 LS0, LS1 and LS2 Pin Setting and Internal Memory Map
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