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參數(shù)資料
| 型號(hào)： | HD6435328F |
| 廠(chǎng)商： | Hitachi,Ltd. |
| 英文描述： | Manual Gives a Hardware Description |
| 中文描述： | 手冊(cè)給出硬件描述 |
| 文件頁(yè)數(shù)： | 13/459頁(yè) |
| 文件大?。?/td> | 1032K |
| 代理商： | HD6435328F |
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Figures
1-1
1-2
1-3
1-4
2-1
2-2
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10 (a) External Access Cycle (Read Access) ·············································································68
3-10 (b) External Access Cycle (Write Access) ············································································69
3-11
Operating States ···············································································································70
3-12
State Transitions ··············································································································71
3-13
Bus-Right Release Cycle (During On-chip Memory Access Cycle) ·······························73
3-14
Bus-Right Release Cycle (During External Access Cycle) ·············································74
3-15
Bus-Right Release Cycle (During Internal CPU Operation) ···········································75
4-1
Types of Factors Causing Exception Handling ································································83
4-2
Reset Vector ·····················································································································86
4-3
Reset Sequence (Minimum Mode, On-Chip Memory) ···················································87
4-4
Reset Sequence (Maximum Mode, External Memory) ···················································88
4-5
Interrupt Sources (and Number of Interrupt Types) ························································91
5-1
Interrupt Controller Block Diagram ················································································98
5-2
Interrupt Handling Flowchart ························································································106
5-3 (a)
Stack before and after Interrupt Exception-Handling (Minimum Mode) ······················107
5-3 (b) Stack before and after Interrupt Exception-Handling (Maximum Mode) ·····················108
5-4
Interrupt Sequence (Minimum Mode, On-Chip Memory) ············································109
5-5
Interrupt Sequence (Maximum Mode, External Memory) ············································110
6-1
Block Diagram of Data Transfer Controller ··································································114
6-2
Flowchart of Data Transfer Cycle ··················································································119
6-3
DTC Vector Table ··········································································································120
6-4
DTC Vector Table Entry ································································································121
6-5
Order of Register Information ·······················································································122
6-6
Use of DTC to Receive Data via Serial Communication Interface ·······························126
7-1
Block Diagram of Wait-State Controller ·······································································128
Block Diagram ···················································································································4
Pin Arrangement (CP-84, Top View) ·················································································5
Pin Arrangement (CG-84, Top View) ················································································6
Pin Arrangement (FP-80A, Top View) ··············································································7
Address Space in Each Mode ··························································································26
Map of Page 0 ··················································································································28
CPU Operating Modes ·····································································································32
Registers in the CPU ········································································································33
Stack Pointer ····················································································································34
Combinations of Page Registers with Other Registers ····················································38
Short Absolute Addressing Mode and Base Register ······················································39
On-Chip Memory Access Timing ····················································································64
Pin States during Access to On-Chip Memory ································································65
Register Field Access Timing ··························································································66
Pin States during Register Field Access ··········································································67
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