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HD404459 Series
114
Item
Symbol
Pin(s)
Min
Typ
Max
Unit
Test Condition
Notes
External clock rise
time
t
CPr
OSC
1
—
—
20
ns
—
3
External clock fall
time
INT
0
–INT
3
,
EVNB
,
WU
–
WU
, EVND
high widths
t
CPf
OSC
1
—
—
20
ns
—
3
t
IH
INT
0
–INT
3
,
WU
0
–
WU
7
,
EVNB
, EVND
INT
0
–INT
3
,
WU
0
–
WU
7
,
EVNB
, EVND
2
—
—
t
cyc
/
t
subcyc
—
4, 7
INT
0
–INT
3
,
EVNB
,
WU
–
WU
7
, EVND
low widths
t
IL
2
—
—
t
cyc
/
t
subcyc
—
4, 7
RESET high width t
RSTH
STOPC
low width
RESET
STOPC
2
—
—
t
cyc
t
RC
ms
—
5
t
STPL
t
RSTf
t
STPr
C
in
1
—
—
—
6
RESET fall time
STOPC
rise time
RESET
STOPC
—
—
20
—
5
—
—
20
ms
—
6
Input capacitance
All pins except
for D
10
D
10
—
—
15
pF
f = 1 MHz, V
in
= 0 V
—
—
15
pF
HD404458, HD404459:
f = 1MHz, V
in
= 0 V
HD4074459:
f = 1 MHz, V
in
= 0 V
—
—
180
pF
Notes: 1. The oscillation stabilization time is the period required for the oscillator to stabilize after V
reaches 1.8 V (2.2 V: HD4074459) at power-on, or after RESET input goes high or
STOPC
input
goes low when stop mode is cancelled. At power-on or when stop mode is cancelled, RESET or
STOPC
must be input for at least t
to ensure the oscillation stabilization time. If using a
ceramic or crystal oscillator, contact its manufacturer to determine the required stabilization time,
since it will depend on the circuit constants and stray capacitances. Set bits 0 and 1 (MIS0,
MIS1) of the miscellaneous register (MIS: $00C) according to the oscillation stabilization time of
the system oscillation.
2. The oscillation stabilization time is the period required for the oscillator to stabilize after V
reaches 1.8 V (2.2 V: HD4074459) at power-on, or after RESET input goes high or
STOPC
input
goes low when stop mode is cancelled. If using a crystal oscillator, contact its manufacturer to
determine the required stabilization time, since it will depend on the circuit constants and stray
capacitances.
3. Refer to figure 88.
4. Refer to figure 89. The t
unit applies when the MCU is in standby or active mode. The t
subcyc
unit applies when the MCU is in watch or subactive mode.
5. Refer to figure 90.
6. Refer to figure 91.
7. In watch or subactive mode, the periods when the
INT
and
WU
–
WU
signals are high and when
these signals are low must be equal to the interrupt frame period or longer.