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參數(shù)資料
| 型號： | HCTS75D |
| 廠商： | Intersil Corporation |
| 英文描述： | Quadruple Bus Buffer Gates With 3- State Outputs 14-CFP -55 to 125 |
| 中文描述： | 輻射加固雙2位雙穩(wěn)態(tài)透明鎖存器 |
| 文件頁數(shù)： | 3/9頁 |
| 文件大?。?/td> | 136K |
| 代理商： | HCTS75D |
472
Specifications HCTS75MS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
(NOTES 1, 2)
CONDITIONS
GROUP
A SUB-
GROUPS
TEMPERATURE
LIMITS
UNITS
MIN
MAX
Propagation Delay
D to Q
TPLH
VCC = 4.5V, VIH = 3.0V,
VIL = 0V
9
+25
o
C
2
19
ns
10, 11
+125
o
C, -55
o
C
2
24
ns
TPHL
VCC = 4.5V, VIH = 3.0V,
VIL = 0V
9
+25
o
C
2
27
ns
10, 11
+125
o
C, -55
o
C
2
35
ns
Propagation Delay
D to Q
TPLH
VCC = 4.5V, VIH = 3.0V,
VIL = 0V
9
+25
o
C
2
23
ns
10, 11
+125
o
C, -55
o
C
2
29
ns
TPHL
VCC = 4.5V, VIH = 3.0V,
VIL = 0V
9
+25
o
C
2
19
ns
10, 11
+125
o
C, -55
o
C
2
22
ns
Propagation Delay
E to Q
TPLH
VCC = 4.5V, VIH = 3.0V,
VIL = 0V
9
+25
o
C
2
21
ns
10, 11
+125
o
C, -55
o
C
2
25
ns
TPHL
VCC = 4.5V, VIH = 3.0V,
VIL = 0V
9
+25
o
C
2
20
ns
10, 11
+125
o
C, -55
o
C
2
23
ns
Propagation Delay
E to Q
TPLH
VCC = 4.5V, VIH = 3.0V,
VIL = 0V
9
+25
o
C
2
24
ns
10, 11
+125
o
C, -55
o
C
2
29
ns
TPHL
VCC = 4.5V, VIH = 3.0V,
VIL = 0V
9
+25
o
C
2
28
ns
10, 11
+125
o
C, -55
o
C
2
34
ns
NOTES:
1. All voltages referenced to device GND.
2. Measurements made with RL = 500
, CL = 50pF, Input TR = TF = 3ns.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
LIMITS
UNITS
MIN
MAX
Capacitance Power
Dissipation
CPD
VCC = 5.0V, f = 1MHz
1
+25
o
C
-
36
pF
1
+125
o
C, -55
o
C
-
51
pF
Input Capacitance
CIN
VCC = 5.0V, f = 1MHz
1
+25
o
C
-
10
pF
1
+125
o
C, -55
o
C
-
10
pF
Pulse Width Time
TW
VCC = 4.5V, VIH = 4.5V,
VIL = 0.0V
1
+25
o
C
-
16
ns
1
+125
o
C, -55
o
C
-
24
ns
Setup Time
TSU
VCC = 4.5V, VIH = 4.5V,
VIL = 0.0V
1
+25
o
C
-
12
ns
1
+125
o
C, -55
o
C
-
18
ns
Hold Time
TH
VCC = 4.5V, VIH = 4.5V,
VIL = 0.0V
1
+25
o
C
-
12
ns
1
+125
o
C, -55
o
C
-
18
ns
Output Transition
Time
TTHL,
TTLH
VCC = 4.5V, VIH = 4.5V,
VIL = 0.0V
1
+25
o
C
15
ns
1
+125
o
C, -55
o
C
22
ns
NOTE:
1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly
tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics.
Spec Number
518625
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| HCTS75DMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Dual 2-Bit Bistable Transparent Latch |
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| HCTS75KMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Dual 2-Bit Bistable Transparent Latch |
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