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參數(shù)資料
| 型號： | HCPMEM-512 |
| 廠商： | Hanbit Electronics Co.,Ltd. |
| 英文描述： | EDO DRAM Board 512Mbyte ( 32M x 144-Bit ) organized as 4Banks of 8Mx144, 4K Ref., 3.3V, ECC |
| 中文描述： | EDO公司的DRAM局512Mbyte（32M的× 144位）籌辦的8Mx144，4K的參考4Banks。，3.3伏，環(huán)境保護運動委員會 |
| 文件頁數(shù)： | 10/21頁 |
| 文件大?。?/td> | 819K |
| 代理商： | HCPMEM-512 |
HANBit HCPMEM-512
URL : www.hbe.co.kr 10
HANBit Electronics Co.,Ltd.
Rev. 1.0 (March, 2002)
Notes:
1. AC measurements assume tT = 2 ns.
2. An initial pause of 200
μ
s is required after power up followed by a minimum of eight initialization cycles (any
combination of cycles containing /RAS-only refresh or /CAS -before-/RAS refresh).
3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference
point only; if tRCD is greater than the specified tRCD (max) limit, than the access time is controlled exclusively
by tCAC .
4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference
point only; if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by
tAA .
5. Either tOED or tCDD must be satisfied.
6. Either tDZO or tDZC must be satisfied.
7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are
measured between VIH (min) and VIL (max).
8. Assumes that tRCD
≤
tRCD (max) and tRAD
≤
tRAD (max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF.
10. Assumes that tRCD
≥
tRCD (max) and tRCD + tCAC (max)
≥
tRAD + tAA (max).
11. Assumes that tRAD
≥
tRAD (max) and tRCD + tCAC (max)
≥
tRAD + tAA (max).
12. Either tRCH or tRRH must be satisfied for a read cycles.
13. tOFF (max), tOEZ (max), tWEZ (max) and tOFR (max) define the time at which the outputs achieve the open
circuit condition and are not referred to output voltage levels.
14. tWCS , tRWD , tCWD , tAWD and tCPW are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only; if tWCS
≥
tWCS (min), the cycle is an early write cycle and the data out
pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD
≥
tRWD (min), tCWD
≥
tCWD
(min), and tAWD
≥
tAWD (min), or tCWD
≥
tCWD (min), tAWD
≥
tAWD (min) and tCPW
≥
tCPW (min), the cycle
is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above
sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate.
15. tDS and tDH are referred to /UCAS and /LCAS leading edge in early write cycles and to /WE leading edge in
delayed write or read-modify-write cycles.
16. tRASP defines /RAS pulse width in EDO page mode cycles.
17. Access time is determined by the longest among tAA , tCAC and tCPA .
18. In delayed write or read-modify-write cycles, /OE must disable output buffer prior to applying data to the device.
19. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output
buffer is turned on and off within a very short time, generally it causes large Vcc /Vss line noise, which causes to
degrade VIH min/VIL max level.
20. tHPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read cycles. If
both write and read operation are mixed in a EDO page mode /RAS cycle (EDO page mode mix cycle (1), (2)),
minimum value of /CAS cycle (tCAS + tCP + 2 tT ) becomes greater than the specified tHPC (min) value. The
value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle (1) and (2).
21. Data output turns off and becomes high impedance from later rising edge of /RAS and /CAS . Hold time and turn
off time are specified by the timing specifications of later rising edge of /RAS and /CAS between tOHR and tOH
and between tOFR and tOFF .
22. tDOH defines the time at which the output level go cross. VOL = 0.8 V, VOH = 2.0 V of output timing reference
level.
23. Before and after self refresh mode, execute CBR refresh to all refresh addresses in or within 64 ms period on the
condition a and b below.
a. Enter self refresh mode within 15.6
μ
s after either burst refresh or distributed refresh at qual interval to all
refresh addresses are completed.
b. Start burst refresh or distributed refresh at equal interval to all refresh addresses within 15.6
μ
s after exiting
from self refresh mode.
24. In case of entering from /RAS -only-refresh, it is necessary to execute CBR refresh before and after self refresh
mode according as note 23.
25. At tRASS > 100
μ
s, self refresh mode is activated, and not activated at tRASS < 10
μ
s. It is undefined within the
range of 10
μ
s
≤
tRASS
≤
100
μ
s. For tRASS
≥
10
μ
s, it is necessary to satisfy tRPS .
26. tASC , tCAH , tRCS , tWCS , tWCH , tCSR , tRPC , tCRP , tCHR , tRCH , tCPA , tCPW , tCWL , tDH , tDS ,
tCHS and tCP are determined by each of /UCAS /LACS independently.
27. XXX : H or L (H: VIH (min)
≤
VIN
≤
VIH (max), L: VIL (min)
≤
VIN
≤
VIL (max))
/////// : Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or
VIL .
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