參數(shù)資料
型號(hào): HCPL0630
英文描述: Dual Channel, High CMR, High Speed, TTL Compatible Optocouplers 8 Pin DIP and SOIC-8
中文描述: 雙通道,高CMR,高速,TTL兼容光耦8引腳DIP和SOIC - 8
文件頁(yè)數(shù): 6/10頁(yè)
文件大?。?/td> 162K
代理商: HCPL0630
6
Parameter
Symbol
Device
Min.
T yp.* Max.
Units
T est Conditions
T
A
= 25
°
C
F ig.
Note
Propagation Delay
Time to High
Output Level
75
ns
t
PLH
20
48
7, 8, 9
3, 6
100
ns
Propagation Delay
Time to Low
Output Level
75
ns
T
A
= 25
°
C
t
PHL
25
50
7, 8, 9
3, 7
100
ns
R
L
= 350
C
L
= 15 pF
Pulse Width
Distortion
|t
PHL
-t
PLH
|
3.5
35
ns
10
13
Propagation Delay
Skew
t
PSK
40
ns
13,14
Output Rise Time
(10-90%)
t
r
24
ns
11
3
Output Fall Time
(90-10%)
t
f
10
ns
11
3
Common Mode
Transient
Immunity at
High Output
Level
HCPL-2630/0630
10,000
V
CM
= 10 V
V
O(MIN)
= 2 V,
R
L
,
I
F
= 0 mA,
T
A
= 25
°
C
|CM
H
|
HCPL-2631/0631
5,000
10,000
V/
μ
s
V
CM
= 50 V
12
3, 8,
10
HCPL-4661/0661 10,000 15,000
V
CM
= 1000 V
Common Mode
Transient
Immunity at
Low Output
Level
HCPL-2630/0630
10,000
V
CM
= 10 V
V
O(MAX)
= 0.8 V,
R
L
,
I
F
= 7.5 mA
T
A
= 25
°
C
|CM
L
|
HCPL-2631/0631
5,000
10,000
V/
μ
s
V
CM
= 50 V
12
3, 9,
10
HCPL-4661/0661 10,000 15,000
V
CM
= 1000 V
Switching Specifications
Over recommended temperature (T
A
= -40
°
C to +85
°
C), V
CC
= 5 V, I
F
= 7.5 mA, unless otherwise
specified.
*All typical values are at V
CC
= 5 V, T
A
= 25
°
C.
Notes:
1. Bypassing of the power supply line is required with a 0.1
μ
F ceramic disc capacitor adjacent to each optocoupler. Total lead
length between both ends of the capacitor and the isolator pins should not exceed 10 mm.
2. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current
does not exceed 15 mA.
3. Each channel.
4. Measured between pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together.
5. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together.
6. The t
propagation delay is measured from the 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the
rising edge of the output pulse.
7. The t
propagation delay is measured from the 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the
falling edge of the output pulse.
8. CM
is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic
state (i.e., V
> 2.0 V).
9. CM
is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic
state (i.e., V
< 0.8 V).
10. For sinusoidal voltages, (|dV
|/dt)
=
π
f
V
(p-p).
11. As illustrated in Figure 15 the V
and GND traces can be located between the input and the output leads to provide
additional noise immunity at the compromise of insulation capability.
12. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage
3000 V
RMS
for 1 second
(Leakage detection current limit, I
5
μ
A).
13. See application section; “Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew” for more information.
14. t
is equal to the worst case difference in t
PHL
and/or t
PLH
that will be seen between units at any given temperature within
the operating condition range.
15. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage
6000 V
RMS
for 1 second
(Leakage detection current limit, I
5
μ
A). This option is valid for HCPL-2630/2631/4661 only.
16. Measured between the LED anode and cathode shorted together and pins 5 through 8 shorted together.
17. Derate linearly above 80
°
C free-air temperature at a rate of 2.7 mW/
°
C for the SOIC-8 package.
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