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參數(shù)資料
| 型號： | HCD66108BP |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Driver IC; Package/Case:16-DIP; Mounting Type:Through Hole |
| 中文描述： | （內存提供165通道的LCD液晶點陣圖形驅動程序） |
| 文件頁數(shù)： | 9/60頁 |
| 文件大?。?/td> | 337K |
| 代理商： | HCD66108BP |
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HD66108
962
Register List
Reg. No.Reg.
1
0
Register Read/
Data Bit Assignment
CS RS 2
Symbol Name
Write 7
6
5
4
3
2
1
0
Busy Time
Notes
1
—
— — — —
Invalid
—
—
1
0
0
— — — AR
Address
R
Busy STBY DISP
Register No.
None
W
0
1
0
0
0
DRAM
Display
memory
R
D7
D6
D5
D4
D3
D2
D1
D0
8 clocks max
2
W
3
0
1
0
0
1
XAR
X
address
R
XAD
None
W
1.5 clocks max
0
1
0
1
0
YAR
Y
address
R
YAD
None
W
1.5 clocks max
0
1
0
1
1
FCR
Control
R
INC
WLS
PON
ROS
DUTY
None
W
0
1
1
0
0
MDR
Mode
R
FFS
DWS
None
W
0
1
1
0
1
CSR
C select
R
EOR
CLN
None
W
0
1
1
1
0
—
Invalid
—
—
0
1
1
1
1
—
Invalid
—
—
Notes: 1. Shaded bits are invalid. Writing 1 or 0 to invalid bits does not affect LSI operation. Reading
these bits returns 0.
2. DRAM is not actually a register but can be handled as one.
3. Setting the WLS bit of control register to 1 invalidates D7 and D6 bits of the display memory
register.
4. DRAM must not be written to or read from until a time period of t
has elapsed rewriting the
DUTY bit of FCR or the FFS bit of MDR. t
can be obtained from the following equation; in
general, a time period of 1 ms or greater is sufficient if the frame frequency is 60–90 Hz.
t
CL1 =
D2
Ni·f
CLK
(kHz)(ms) ................ Equation
D2 (duty correction value): 192 (duty = 1/32, 1/34, or 1/36)
128 (duty = 1/48 or 1/50)
96 (duty = 1/64 or 1/66)
Ni (frequency-division ratio specified by the mode register’s FFS bits):
2, 1, 1/2, 1/3, 1/4, 1/6, or 1/8
Refer to “6. Clock and Frame Frequency.”
f
CLK
: Input clock frequency (kHz)
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