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參數(shù)資料
| 型號： | HCD66108BP |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Driver IC; Package/Case:16-DIP; Mounting Type:Through Hole |
| 中文描述： | （內(nèi)存提供165通道的LCD液晶點陣圖形驅(qū)動程序） |
| 文件頁數(shù)： | 58/60頁 |
| 文件大?。?/td> | 337K |
| 代理商： | HCD66108BP |
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HD66108
1011
AC Characteristics (2) (V
CC
= 2.7 to 4.5V, GND = 0V, Ta = –20 to +75°C, unless otherwise noted)
1. CPU Bus Timing (Figure 37)
Item
5'
high-level pulse width
5'
low-level pulse width
:5
high-level pulse width
:5
low-level pulse width
:5
–
5'
high-level pulse width
&6
RS setup time
&6
RS hold time
Write data setup time
Write data hold time
Read data output delay time
Read data hold time
External clock cycle time
External clock high-level pulse width
External clock low-level pulse width
External clock rise and fall time
Note: Measured by test circuit 2 (Figure 39).
Symbol
t
WRH
t
WRL
t
WWH
t
WWL
t
WWRH
t
AS
t
AH
t
DSW
t
DHW
t
DDR
t
DHR
t
CYC
t
WCH
t
WCL
t
r
, t
f
Min
1.0
1.0
1.0
1.0
1.0
0.5
0.1
1.0
0
—
20
1.6
0.7
0.7
—
Max
—
—
—
—
—
—
—
—
—
0.5
—
5.0
—
—
0.1
Unit
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
μs
μs
μs
μs
Note
Note
2. LCD Interface Timing (Figure 38)
Item
0
/S = 0 CL1 High-level pulse width
CL1 Low-level pulse width
FLM Delay time
FLM Hold time
M output delay time
0
/S = 1 CL1 High-level pulse width
CL1 Low-level pulse width
FLM Delay time
FLM Hold time
M delay time
Notes: 1. When R
OSC
is 91 k
(V
CC
= 4.0 to 6V) or 75 k
(V
CC
= 2.7 to 4.0V) and bits FFS are set for 1.
2. When bits FFS are set for 1 or 2. The value is 19
×
t
CYC
in other cases.
3. When bits FFS are set for 1 or 2. The value is 8.5
×
t
CYC
in other cases.
4. Measured by test circuit 2 (Figure 39).
Symbol
t
WCH1
t
WCL1
t
DFL1
t
HFL1
t
DMO1
t
WCH2
t
WCL2
t
DFL2
t
HFL2
t
DMI
Min
35
35
–2.0
–2.0
–2.0
35
11
×
t
CYC
–2.0
–2.0
–2.0
Max
—
—
+2.0
+2.0
+2.0
—
—
1.5
×
t
CYC
+2.0
+2.0
Unit
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
Notes
1, 4
1, 4
4
4
4
4
2, 4
3, 4
4
4
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