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參數(shù)資料
| 型號： | HCD40C4344R |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 4-bit HMCS400-series microcomputer(4位單片微計算機) |
| 中文描述： | 4位HMCS400系列微電腦（4位單片微計算機） |
| 文件頁數(shù)： | 65/100頁 |
| 文件大小： | 610K |
| 代理商： | HCD40C4344R |
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HD404344R Series/HD404394 Series
65
Output Level Control During Idle States:
The output level of the SO pin can be set during either STS
wait state or transmit clock wait state by software. During idle states, the output level is controlled by
writing to bit 1 (PMRC1) of port mode register C (PMRC: $025). An example of output level control
during idle states is shown in figure 43. During transfer state, output level control cannot be executed.
State
MCU reset
PMRA write
SMR write
PMRC write
SCK
pin
(input)
STS wait state
Transmit clock
wait state
Transfer state
Transmit clock
wait state
STS wait state
Port selection
External clock selection
Output level control in
idle states
Dummy write for
state transition
Output level control in
idle states
Data write for transmission
Undefined
LSB
MSB
Flag reset at transfer completion
External clock mode
State
MCU reset
PMRA write
SMR write
PMRC write
STS wait state
Transfer state
Transmit clock
wait state
STS wait state
Port selection
Internal clock selection
Output level control in
idle states
Data write for transmission
Output level control in
idle states
Undefined
LSB
MSB
Flag reset at transfer completion
Internal clock mode
instruction
write
SRL, SRU
STS
SO pin
IFS
SCK
pin
(output)
instruction
write
SRL, SRU
STS
SO pin
IFS
Figure 43 Example of Serial Interface Operation Sequence
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