參數(shù)資料
型號(hào): HCC4029B
廠商: 意法半導(dǎo)體
元件分類(lèi): 通用總線功能
英文描述: BINARY OR BCD DECADE PRESETTABLE UP/DOWN COUNTER
中文描述: 二進(jìn)制或BCD十年預(yù)置加/減計(jì)數(shù)器
文件頁(yè)數(shù): 8/13頁(yè)
文件大小: 295K
代理商: HCC4029B
APPLICATIONS
Conversion of Clock up, Clock Down Input Sig-
nals to Clock and Up/Down Inputs Signals.
Cascading Counter Packages.
The
HCC/HCF4029B
CLOCK and UP/DOWN in-
puts are used directly inmost applications. In appli-
cations where CLOCK UP and CLOCK DOWN
inputs
are
provided,
HCC/HCF4029B
CLOCK and UP/DOWN inputs
can easilybe realized by use of the circuit.
HCC/HCF4029B
changes count on positive transi-
tions of CLOCK UP or CLOCK DOWN inputs. For
the gateconfiguration shown below, when counting
up the CLOCK DOWN input must be maintained
high and conversely when counting down the
CLOCKUP input must be maintained high.
conversion
to
the
*
CARRY-OUT lines at the 2nd, 3rd, et., stages may have a negative-going glitch pulse resulting from differential delays of different
HCC/HCF4029B
IC’s.Thesenegative-going glitchesdo notaffect proper
HCC/HCF4029B
operation. However,if the CARRY-OUTsignals
are used to trigger otheredge-sensitive logicdevices, suchasFF’sor counters, theCARRY-OUTsignals shouldbe gated withtheclocksignal
using a 2-input NOR gate suchas
HCC/HCF4001B
.
RippleClocking Mode: The Up/Down controlcan be changed at any count. Theonlyrestriction on changing the Up/Down control is thatthe
clock inputto the firstcounting stage must behigh.
HCC/HCF4029B
8/13
相關(guān)PDF資料
PDF描述
HCF4029BC1 BINARY OR BCD DECADE PRESETTABLE UP/DOWN COUNTER
HCC4029BF Dual Line Receiver 14-SOIC 0 to 70
HCF4029BEY Quadruple Differential Line Receiver 16-PDIP 0 to 70
HCF4029BM1 BINARY OR BCD DECADE PRESETTABLE UP/DOWN COUNTER
HCC4030B QUAD EXCLUSIVE-OR GATE
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