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參數(shù)資料
| 型號： | HCC4029B |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | 通用總線功能 |
| 英文描述： | BINARY OR BCD DECADE PRESETTABLE UP/DOWN COUNTER |
| 中文描述： | 二進(jìn)制或BCD十年預(yù)置加/減計數(shù)器 |
| 文件頁數(shù)： | 6/13頁 |
| 文件大小： | 295K |
| 代理商： | HCC4029B |
DYNAMIC ELECTRICAL CHARACTERISTICS
(T
amb
= 25
o
C, C
L
= 50 pF, R
L
= 200 K
,
typical temperature coefficent for all V
DD
values is 03 %/
o
C, all input rise and fall times= 20 ns)
Symbol
Parameter
Test Conditions
Value
Typ.
250
120
90
280
130
95
100
50
40
90
45
30
Unit
V
DD
(V)
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
Min.
Max.
500
240
180
560
260
190
200
100
80
180
90
60
15
15
15
60
20
12
340
140
100
t
PLH
t
PHL
Propagation Delay Time (Q Outputs)
ns
t
PLH
t
PHL
Propagation Delay Time (Carry Output)
ns
t
TLH
t
THL
Transition Time (Q Outputs, Carry Output)
ns
t
W
Minimum Clock Pulse Width
ns
t
r
, t
f
**
Clock Rise and Fall Time
μ
s
t
setup
*
Minimum Setup Time (Carry Input)
30
10
6
170
70
50
4
8
11
ns
t
setup
Minimum Setup Time (B/D or UD)
f
max
Maximum Clock Input Frequency
2
4
MHz
5.5
PRESET ENABLE
t
PLH
t
PHL
Propagation Delay Time (Q Outputs)
5
10
15
5
10
15
5
10
15
5
10
15
235
100
80
320
145
105
65
35
25
100
55
40
470
200
160
640
290
210
130
70
50
200
110
80
ns
t
PLH
t
PHL
Propagation Delay Time (Carry Output)
t
W
Minimum Preset Enable (Pulse Width)
ns
t
rem
*
Minimum Preset Enable (Removal Time)
ns
CARRY INPUT
t
PHL
t
PLH
Propagation Delay Time (Carry Output)
5
10
15
5
10
15
5
10
15
170
70
50
25
15
12
100
35
30
340
140
100
50
30
25
200
70
60
ns
t
setup
***
Minimum Setup Time (Carry In)
ns
t
hold
Minimum Hold Time (Carry In)
*
** If more than one unitis cascated in theparallel clocked application trshould be made less than or equalto the sumof thefixed propagation
delay at 15pF and thetransition time ofthecarry output drivingstage for theestimated capacitance load.
*** FromCarry in toClock Edge.
From Up/Down, Binary/Decade, CarryIn or Preset Enable Control Inputs toClock Edge
HCC/HCF4029B
6/13
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HCF4029BC1 | BINARY OR BCD DECADE PRESETTABLE UP/DOWN COUNTER |
| HCC4029BF | Dual Line Receiver 14-SOIC 0 to 70 |
| HCF4029BEY | Quadruple Differential Line Receiver 16-PDIP 0 to 70 |
| HCF4029BM1 | BINARY OR BCD DECADE PRESETTABLE UP/DOWN COUNTER |
| HCC4030B | QUAD EXCLUSIVE-OR GATE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HCC4029BD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| HCC4029BF | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:BINARY OR BCD DECADE PRESETTABLE UP/DOWN COUNTER |
| HCC4029BK | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| HCC4030B | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:RadHardened high voltage complementary MOS logic series |
| HCC4030BD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
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