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參數(shù)資料
| 型號： | HCC4015BF |
| 廠商： | 意法半導體 |
| 元件分類： | FIFO |
| 英文描述： | 65536 x 18 Synchronous FIFO Memory 80-LQFP 0 to 70 |
| 中文描述： | 雙4級靜態(tài)移位寄存器與串行輸入/并行輸出 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 281K |
| 代理商： | HCC4015BF |
DYNAMIC ELECTRICAL CHARACTERISTICS
(T
amb
= 25
°
C, C
L
= 50 pF, R
L
= 200 k
,
typical temperature coefficient for all V
DD
values is 0.3 %/
°
C, all input rise and fall times = 20 ns)
Value
Typ.
Symbol
Parameter
Test Conditions
V
DD
(V)
Min.
Max.
Unit
CLOCKED OPERATION
t
PLH
, t
PHL
Propagation Delay Time
(carry out or decoded out lines)
5
160
80
60
100
50
40
6
12
17
90
40
25
320
160
120
200
100
80
ns
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
t
THL
, t
TLH
Transition Time
(carry out or decoded out lines)
ns
f
CL
Maximum Clock Input Frequency
3
6
MHz
8.5
180
80
50
t
W
Clock Pulse Width
ns
t
r
, t
f
*
Clock Input Rise or Fall Time
15
15
15
μ
s
t
setup
Data Setup Time
70
40
30
35
20
15
ns
RESET OPERATION
t
PLH
, t
PHL
Propagation Delay Time
5
200
100
80
100
40
30
400
200
160
ns
10
15
5
10
15
t
W
Reset Pulse Width
200
80
60
ns
* Ifmore than unit is cascaded intheparallel clocked application, t
CL should bemade lessthan orequa tothesum of the fixedpropagation delay
at 15pF and thetransition time of thecarry output driving stagefor the estimated capacitive load.
HCC/HCF4015B
5/12
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