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參數(shù)資料
| 型號(hào)： | HC652 |
| 廠商： | System Logic Semiconductor Co., Ltd. |
| 英文描述： | EPROM IC; Memory Size:128Kbit; Memory Configuration:16K x 8; Access Time, Tacc:250ns; Package/Case:28-DIP; EPROM Type:Parallel UV Erasable; Supply Voltage Nom, Vcc:5V; Mounting Type:Through Hole; Voltage Rating:5V |
| 中文描述： | 八路三態(tài)總線收發(fā)器和D觸發(fā)器 |
| 文件頁(yè)數(shù)： | 5/9頁(yè) |
| 文件大?。?/td> | 79K |
| 代理商： | HC652 |
SL74HC652
S ystem Logic
Semiconductor
SLS
TIMING REQUIREMENTS
(Input t
r
=t
f
=6.0 ns)
V
CC
Guaranteed Limit
Symbol
Parameter
V
25
°
C to-55
°
C
≤
85
°
C
≤
125
°
C
Unit
t
su
Minimum Setup Time, Input A to
A-to-B Clock (or Input B to B-to-A
Clock) (Figure 7)
2.0
4.5
6.0
50
10
9
65
13
11
75
15
13
ns
t
h
Minimum Hold Time, A-to-B Clock to
Input A (or B-to-A Clock to
Input B) (Figure 7)
2.0
4.5
6.0
25
5
5
30
6
5
40
8
7
ns
t
w
Minimum Pulse Width, A-to-B Clock
(or B-to-A Clock)
(Figure 7)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
t
r
, t
f
Maximum Input Rise and Fall Times
(Figures 2 and 3)
2.0
4.5
6.0
1000
500
1000
500
400
1000
500
400
ns
TIMING DIAGRAM
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