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參數(shù)資料
| 型號： | HC652 |
| 廠商： | System Logic Semiconductor Co., Ltd. |
| 英文描述： | EPROM IC; Memory Size:128Kbit; Memory Configuration:16K x 8; Access Time, Tacc:250ns; Package/Case:28-DIP; EPROM Type:Parallel UV Erasable; Supply Voltage Nom, Vcc:5V; Mounting Type:Through Hole; Voltage Rating:5V |
| 中文描述： | 八路三態(tài)總線收發(fā)器和D觸發(fā)器 |
| 文件頁數(shù)： | 4/9頁 |
| 文件大?。?/td> | 79K |
| 代理商： | HC652 |
SL74HC652
S ystem Logic
Semiconductor
SLS
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Guaranteed Limit
Symbol
Parameter
V
25
°
C to
-55
°
C
≤
85
°
C
≤
125
°
C
Unit
t
PLH
, t
PHL
Maximum Propagation Delay, Input A to Output B
(or Input B to Output A)
(Figures 2,3 and 9)
2.0
4.5
6.0
180
36
31
225
45
38
270
54
46
ns
t
PLH
, t
PHL
Maximum Propagation Delay, A-to-B Clock to
Output B (or B-to-A Clock to Output A)
(Figures 1 and 9)
2.0
4.5
6.0
240
48
41
300
60
51
360
72
61
ns
t
PLH
, t
PHL
Maximum Propagation Delay, A-to-B Source to
Output B (or B-to-A Source to Output A) (Figures
4 and 9)
2.0
4.5
6.0
220
44
37
275
55
47
330
66
56
ns
t
PLZ
, t
PHZ
Maximum Propagation Delay , Direction or Output
Enable to Output A or B
(Figures 5,6 and 10)
2.0
4.5
6.0
170
34
29
215
43
37
255
51
43
ns
t
PZL
, t
PZH
Maximum Propagation Delay , Direction or Output
Enable to Output A or B
(Figures 5,6 and 10)
2.0
4.5
6.0
180
36
31
225
45
38
270
54
46
ns
t
TLH
, t
THL
Maximum Output Transition Time, Any Output
(Figure 2)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
C
IN
Maximum Input Capacitance
-
10
10
10
pF
C
OUT
Maximum Three-State I/O Capacitance
(Output in High-Impedance State
-
15
15
15
pF
Power Dissipation Capacitance (Per Channel)
Typical @25
°
C,V
CC
=5.0 V
C
PD
Used to determine the no-load dynamic power
consumption:
P
D
=C
PD
V
CC
2
f+I
CC
V
CC
60
pF
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