
67
same amount to account for resistors R
12
and R
14
.
The net effect cancels out the voltage drop across the feed
resistors. By nullifying the effects of the feed resistors the
feedback circuitry becomes relatively easy to match the
impedance at points “A” and “B”.
IMPEDANCE MATCHING DESIGN EQUATIONS
Matching the impedance of the SLIC to the load is
accomplished by writing a loop equation starting at V
D
and
going around the loop to V
C
. The loop equation to match the
impedance of any load is as follows (Note: V
RX
= 0 for this
analysis):
R
8
R
9
Equation 19 can be separated into two terms, the feedback
(-8R
S
(R
8
/R
9
)) and the loop impedance (+4R
S
+R
L
).
The result is shown in Equation 20. Figure 4 is a schematic
representation of Equation 15.
To match the impedance of the SLIC to the impedance of the
load, set:
If R
9
is made to equal 8R
S
then:
2V
DC
R
R
L
R
9
R
8
I
L
+
-
I
L
+
-
I
L
+
-
I
L
+
-
I
L
+
-
-R
S
I
L
R
11
= R
12
= R
13
= R
14
= R
S
+R
S
I
L
4R
S
I
L
-
4R
S
I
L
+
4R
S
I
L
2R
R
9
R
8
I
OUT1
=
I
R
GROUNDED FOR AC ANALYSIS
1V
P
V
TR
V
IN
VC
4
–
RSIL
-------
VRX
+
=
VD
4RSIL
-------
VRX
–
=
I
L
+
-
TIP
B
A
R
9
R
8
IR
4
–
-----------------------------
(
)
-------
------------
+
=
FIGURE 3. AC VOLTAGE GAIN AND IMPEDANCE MATCHING
OUT1
V
BAT
2
-
+
+
-
V
C
V
D
R
14
R
12
R
11
R
13
90k
90k
R
R/2
+
-
+
-
R
+
-
2
+
-
+
-
+
-
+
-
RING
+
-
R/20
V
RING
V
RX
V
TX
-IN
1
+
-
-
+
4R
S
I
L
–
------
2R
S
I
L
V
IN
–
+
+
R
L
I
L
2R
S
I
L
4R
S
I
L
–
R
8
R
9
------
0
=
+
(EQ. 17)
V
IN
8R
S
I
L
–
R
8
R
9
------
4R
S
I
L
R
L
I
L
+
+
=
(EQ. 18)
V
IN
I
L
8R
S
–
R
8
R
9
------
4R
S
R
L
+
+
=
(EQ. 19)
V
IN
I
L
------------
8
–
R
S
R
8
R
9
------
4R
S
R
L
+
+
=
(EQ. 20)
V
IN
R
L
8RS
-------
4RS
+
LOAD
SLIC
FIGURE 4. SCHEMATIC REPRESENTATION OF EQUATION 20
+
R
L
8R
S
R
8
R
9
------
4R
S
+
=
(EQ. 21)
R
L
R
8
4R
S
+
=
(EQ. 22)
HC5517