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參數(shù)資料
| 型號(hào)： | HC55130 |
| 廠商： | Intersil Corporation |
| 英文描述： | Ultra Low Power SLICs.(超低功耗用戶線路接口電路) |
| 中文描述： | 超低功耗SLIC組件。（超低功耗用戶線路接口電路） |
| 文件頁(yè)數(shù)： | 4/7頁(yè) |
| 文件大?。?/td> | 83K |
| 代理商： | HC55130 |
4-4
An equation for the system transmit gain is achieved by
substituting Equation 20 into Equation 22.
(
0
To achieve a Transmit Gain of one (V
PCMOUT
/ V
2W
), make
R
f
= Z
O
and R
a
= (Z
0
-2R
P
). Actual values of R
a1
and R
f
were multiplied by 100 to reduce loading effects on the GSX
opamp.
Transhybrid Balance G(4-4)
Transhybrid balance is a measure of how well the input
signal is canceled (that being received by the SLIC) from the
transmit signal (that being transmitted from the SLIC to the
CODEC). Without this function, voice communication would
be difficult because of the echo.
The signals at V
PWRO+
and V
TX
(Figure 3) are opposite in
phase. Transhybrid balance is achieved by summing two
signals that are equal in magnitude and opposite in phase
into the GSX amplifier.
Transhybrid balance is achieved by summing the PWRO+
signal with the output signal from the UniSLIC14 when
proper gain adjustments are made to match V
PWRO+
and
V
TX
magnitudes.
For discussion purpose, the GSX amplifier is redrawn with
the external resistors in Figure 4.
R
a2
V
PWRO+
The gain through the GSX amplifier from V
PWRO+
is set by
resistors R
a2
and R
fr
.The gain through the GSX amplifier
from V
TX
is set by resistors R
a1
and R
f
.
Transhybrid balance is achieved by adjusting the magnitude
from both V
PWRO+
and V
TX
so their equal to each other.
Reference Design of the UniSLIC14 and
the TCM38C17 With a 600
Load
The design criteria is as follows:
4-wire to 2-wire gain (VP
CMIN
to V
2W
) equal 0dB
2-wire to 4-wire gain (V
2W
to VP
CMOUT
) equal 0dB
Two Wire Return Loss greater than -30dB (200Hz to
4kHz)
Rp = 30
Figure 5 gives the reference design using the Intersil
UniSLIC14 and the Texas Instruments TCM38C17 Quad
Combo. Also shown in Figure 5 are the voltage levels at
specific points in the circuit.
Impedance Matching
The 2-wire impedance is matched to the line impedance Z
0
using Equation 1, repeated here in Equation 24.
For a line impedance of 600
, Z
T
equals:
Z
T
The closest standard value for Z
T
is 107k
.
Transhybrid Balance (Z
L
= 600
)
The internal GSX amplifier of the TCM38C17 is used to
perform the transhybrid balance function. Transhybrid
balance is achieved by summing two signals that are equal
in magnitude and opposite in phase into the GSX amplifier.
From Equation 23, repeated here in Equation 26, a Transmit
Gain (V
PCMOUT
/ V
2W
) of one is achieved if we make
R
f
= Z
O
and R
a1
= (Z
0
-2R
P
).
V
Z
- 2R
0
Actual values of R
a1
and R
f
were multiplied by 100 to reduce
loading effects on the GSX op-amp.
Closest standard value for R
f
is 60.4k
Closest standard value for R
a1
is 53.6k
The TCM38C17 receive gain is programmed to 1.0 by
maximizing R
1
and minimizing R
2
resistor values (Figure 2).
The gain from PWRO+/V
RX
through the SLIC at V
TX
is 1.1
(Eq. 31 in the Intersil UniSLIC14 data sheet).
To achieve transhybrid balance from the PWRO+ pin to
PCMOUT set R
a2
= R
a1
x 0.9.
(
)
0.9
(
)
48.24K
=
=
Closest standard value for R
a2
= 48.6k
.
Specific Implementation for China
The design criteria for a China specific solution are as
follows:
Desired line circuit impedance is 200 + 680//0.1
μ
F
Receive gain (V
2W
/V
PCMIN
) is -3.5dB
Transmit gain (V
PCMOUT
/V
2W
) is 0dB
0dBm0 is defined as 1mW into the complex impedance at
1020Hz
R
p
= 30
V
PCMOUT
V
–
TX
R
f
a1
----------
=
(EQ. 22)
G
2
4
–
V
2W
----------------------------
=
Z
- 2R
-----------------------------
)
R
f
a1
----------
=
(EQ. 23)
GSX
-
+
R
a1
R
f
ANLGIN+
V
GSX
FIGURE 4. TRANSHYBRID BALANCE CIRCUIT
ANLGIN-
V
TX
Z
T
200
Z
TR
2R
P
–
(
)
=
(EQ. 24)
200
600
60
–
(
)
108k
=
=
(EQ. 25)
V
PCMOUT
(
)
------------------------------------------
R
f
a1
----------
=
(EQ. 26)
R
f
Z
0
=
600 100
)
60k
=
=
(EQ. 27)
R
a1
Z
0
- 2R
P
(
)
=
600 - 60
(
)
100
(
)
54k
=
=
(EQ. 28)
R
a2
53.6K
(EQ. 29)
Application Note 9903
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HC55130IB | 制造商:Rochester Electronics LLC 功能描述:LOW PWR SLIC,63DB BALANCE - Bulk |
| HC55130IB96 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Low Power Universal SLIC Family |
| HC55130IBZ | 功能描述:電信線路管理 IC LW PWR SLIC 63DB BALANCE RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| HC55130IBZ96 | 功能描述:電信線路管理 IC LW PWR SLIC 63DB BALANCE RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| HC55130IM | 制造商:Rochester Electronics LLC 功能描述:LOW PWR SLIC,63DB BALANCE - Bulk 制造商:Harris Corporation 功能描述: |
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