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參數(shù)資料
| 型號： | HC55120CMZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 14/36頁 |
| 文件大小： | 0K |
| 描述： | IC SLIC UNIVERSAL LP 28-PLCC |
| 標準包裝： | 37 |
| 系列： | UniSLIC14 |
| 功能： | 用戶線路接口概念（SLIC） |
| 電路數(shù)： | 1 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 電流 - 電源： | 2.25mA |
| 功率（瓦特）： | 1.5W |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應商設備封裝： | 28-PLCC（11.51x11.51） |
| 包裝： | 管件 |
| 包括： | 電池跟蹤抗削頂失真，回路和接地鍵檢測，振鈴控制 |
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21
FN4659.13
June 1, 2006
low at zero voltage crossing of the ring signal. This pulse
should have a rise and fall time <400
s and a minimum
pulse width of 2ms.
Zero ring current detection is performed automatically inside
the SLIC. This feature de-energizes the ring relay slightly
before zero current occurs to partially compensate for the
delay in the opening of the relay.
The SHD output will go low when the subscriber goes off
hook. Once SHD is activated, an internal latch will prohibit
the re-ringing of the line until the ringing code is removed
and then reapplied.
The state prior to ringing the phone, can not be the Reverse
Active State. In the reverse active state the polarity of the
voltage on the CRT_REV_LVM capacitor, will make it appear
as if the subscriber is off hook. This subsequently will
activate an internal latch prohibiting the ringing of the line.
The GKD_LVM output is disabled (TTL high level) during the
ringing state. Reference the Section titled “Ringing the
Phone” for more information.
Forward Active State (C3 = 0, C2 = 1, C1 = 0)
In this state, the SLIC is fully functional. The tip voltage is more
positive than the ring voltage. The tip and ring output voltages
are an unbalanced DC feed, reference Figure 13. Both SHD
and GKD supervisory functions are active. Reference the
section titled “DC Feed Curve” for more information.
Test Active State (C3 = 0, C2 = 1, C1 = 1)
Proper operation of the Test Active State requires the
previous state be the Forward Active state to determine the
on hook or off hook status of the line. In this state, the SLIC
can perform two different tests.
If the subscriber is on hook when the state is entered, a
loopback test is performed by switching an internal 600
resistor between tip and ring. The current flows through the
internal 600
is unidirectional via blocking diodes. (Cannot be
used in reverse.) When the loopback current flows, the SHD
output will go low and remain there until the state is exited. This
is intended to be a short test since the ability to detect
subscriber off hook is lost during loopback testing. Reference
the section titled “Loopback Tests” for more information.
If the subscriber is off hook when the state is entered, a Line
Voltage Measurement test is performed. The output of the
GKD_LVM pin is a pulse train. The pulse width of the active low
portion of the signal is proportional to the voltage across the tip
and ring pins. If the loop length is such that the SLIC is
operating in constant current, the tip to ring voltage can be used
to determine the length of the line under test. The longer the
line, the larger the tip to ring voltage and the wider the pulse.
This relationship can determine the length of the line for setting
gains in the system. Reference the section titled “Operation of
Line Voltage Measurement” for more information.
Tip Open State (C3 = 1, C2 = 0, C1 = 0)
In this state, the tip output is in a high impedance state
(>250k
) and the ring output is capable of full operation, i.e.
has full longitudinal current capability. The Tip Open/Ground
Start state is used to interface to a PBX incoming 2-wire
trunk line. When a ground is applied through a resistor to the
ring lead, this current is detected and presented as a TTL
logic low on the SHD and GKD_LVM output pins.
Reserved (C3 = 1, C2 = 0, C1 = 1)
This state is undefined and reserved for future use.
Reverse Active State (C3 = 1, C2 = 1, C1 = 0)
In this state, the SLIC is fully functional. The ring voltage is
more positive than the tip voltage. The tip and ring output
voltages are an unbalanced DC feed, reference Figure 13.
The polarity reversal time is determined by the RC time
constant of the RSYNC_REV resistor and the
CRT_REV_LVM capacitor. Capacitor CRT_REV_LVM
performs three different functions: Ring trip filtering, polarity
reversal time and line voltage measurement. It is
recommended that programming of the reversal time be
accomplished by changing the value of RSYNC_REV resistor
(see Figure 18). The value of RSYNC_REV resistor is limited
between 34.8K (10ms) and 73.2k (21ms). Equation 39 gives
the formula for programming the reversal time.
Both SHD and GKD supervisory functions are active.
Reference the section titled “Polarity Reversal” for more
information.
Test Reversal Active State (C3 = 1, C2 = 1, C1 = 1)
Proper operation of the Test Reversal Active State requires
the previous state be the Reverse Active state to determine
the on hook or off hook status of the line.
If the subscriber is on hook when the state is entered, the
SLIC’s tip and ring voltages are the same as the Reverse
Active state. The SHD output will go low when the subscriber
goes off hook and the GKD_LVM output is disabled (TTL
level high). (Note: operation is the same as the Reverse
Active state with the GKD_LVM output disabled.)
If the subscriber is off hook when the state is entered, a
Line Voltage Measurement test is performed.
The output of the GKD_LVM pin is a pulse train. The pulse width
of the active low portion of the signal is proportional to the voltage
across the tip and ring pins. If the loop length is such that the
SLIC is operating in constant current mode, the tip to ring voltage
can be used to determine the length of the line under test. The
longer the line, the larger the tip to ring voltage and the wider the
pulse. This relationship can determine the length of the line for
setting gains in the system. Reference the section titled
“Operation of Line Voltage Measurement” for more information.
RSYNC
REV
–
3.47k
ReversalTime ms
()
×
=
(EQ. 39)
HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150
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相關代理商/技術參數(shù) |
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| HC55121 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Low Power Universal SLIC Family |
| HC55121IB | 制造商:Rochester Electronics LLC 功能描述:LOW POWER,SLIC,POL/REV/METERING,5301B BALANCE - Bulk |
| HC55121IBZ | 功能描述:電信線路管理 IC LW PWR SLIC POL/REV/MTRING 5301B RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| HC55121IM | 制造商:Rochester Electronics LLC 功能描述:LOW PWR SLIC,POL REV/METERING,53DB BALANCE - Bulk |
| HC55121IMZ | 功能描述:電信線路管理 IC LW PWR SLIC POLV/MTRING 53DB RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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