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參數(shù)資料
| 型號： | HC165 |
| 廠商： | System Logic Semiconductor Co., Ltd. |
| 英文描述： | 8-Bit Serial or Parallel-Input/ Serial-Output Shift Register |
| 中文描述： | 8位串行或并行輸入/串行輸出移位寄存器 |
| 文件頁數(shù)： | 5/7頁 |
| 文件大?。?/td> | 67K |
| 代理商： | HC165 |
SL74HC165
S ystem Logic
Semiconductor
SLS
TIMING REQUIREMENTS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Guaranteed Limit
Symbol
Parameter
V
25
°
C to
-55
°
C
≤
85
°
C
≤
125
°
C
Unit
t
SU
Minimum Setup Time, Parallel
Data Inputs to Serial
Shift/Parallel Load (Figure 4)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
t
SU
Minimum Setup Time, Input S
A
to Clock (or Clock Inhibit)
(Figure 5)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
t
SU
Minimum Setup Time, Serial
Shift/Parallel Load to Clock (or
Clock Inhibit) (Figure 6)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
t
SU
Minimum Setup Time, Clock to
Clock Inhibit (Figure 7)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
t
h
Minimum Hold Time, Serial
Shift/Parallel Load to Parallel
Data Inputs (Figure 4)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
ns
t
h
Minimum Hold Time, Clock (or
Clock Inhibit) to Input S
A
(Figure 5)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
ns
t
h
Minimum Hold Time, Clock (or
Clock Inhibit) to Serial
Shift/Parallel Load (Figure 6)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
ns
t
rec
Minimum Recovery Time,
Clock to Clock Inhibit
(Figure 7)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
t
w
Minimum Pulse Width, Clock
(or Clock Inhibit) (Figure 1)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
t
w
Minimum Pulse Width, Serial
Shift/Parallel Load (Figure 2)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
t
r,
t
f
Maximum Input Rise and Fall
Times (Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
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