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參數(shù)資料
| 型號(hào)： | HC165 |
| 廠商： | System Logic Semiconductor Co., Ltd. |
| 英文描述： | 8-Bit Serial or Parallel-Input/ Serial-Output Shift Register |
| 中文描述： | 8位串行或并行輸入/串行輸出移位寄存器 |
| 文件頁(yè)數(shù)： | 4/7頁(yè) |
| 文件大?。?/td> | 67K |
| 代理商： | HC165 |
SL74HC165
S ystem Logic
Semiconductor
SLS
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Guaranteed Limit
Symbol
Parameter
V
25
°
C to
-55
°
C
≤
85
°
C
≤
125
°
C
Unit
f
max
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 8)
2.0
4.5
6.0
6.0
30
35
4.8
24
28
4.0
20
24
MHz
t
PLH
, t
PHL
Maximum Propagation Delay, Clock (or Clock
Inhibit) to Q
H
or Q
H
(Figures 1 and 8)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
t
PLH
, t
PHL
Maximum Propagation Delay , SerialShift./.Parallel
Load to Q
H
or Q
H
(Figures 2 and 8)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
t
PLH
, t
PHL
Maximum Propagation Delay, Input H to Q
H
or Q
H
(Figures 3 and 8)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
t
TLH
, t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 8)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
C
IN
Maximum Input Capacitance
-
10
10
10
pF
Power Dissipation Capacitance (Per Package)
Typical @25
°
C,V
CC
=5.0 V
C
PD
Used to determine the no-load dynamic power
consumption:
P
D
=C
PD
V
CC
2
f+I
CC
V
CC
85
pF
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|---|---|
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