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參數(shù)資料
| 型號(hào)： | HB52RF1289E2-75B |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | x72 SDRAM Module |
| 中文描述： | 128M X 72 SYNCHRONOUS DRAM MODULE, 6.3 ns, DMA168 |
| 封裝： | DIMM-168 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 161K |
| 代理商： | HB52RF1289E2-75B |
HB52RF1289E2-75B
Data Sheet E0018H10
12
AC Characteristics
(Ta = 0 to 55°C, V
CC
= 3.3 V ± 0.3 V, V
SS
= 0 V) (cont)
HB52RF1289E2-75B
PC133
CE
latency = 4
PC100
CE
latency = 3
Parameter
Symbol
PC100
Symbol Min
Max
Min
Max
Unit
Notes
Command setup time
t
CS
t
CH
t
RC
Tsi
1.9
—
2.6
—
ns
1
Command hold time
Thi
1.5
—
1.6
—
ns
1, 5
Ref/Active to Ref/Active command
period
Trc
67.5
—
70
—
ns
1
Active to precharge command period t
RAS
Active command to column
command (same bank)
Tras
45
120000 50
120000 ns
1
t
RCD
Trcd
20
—
20
—
ns
1
Precharge to active command period t
RP
Write recovery or data-in to
precharge lead time
Trp
20
—
20
—
ns
1
t
DPL
Tdpl
7.5
—
10
—
ns
1
Active (a) to Active (b) command
period
t
RRD
Trrd
15
—
20
—
ns
1
Transition time (rise to fall)
t
T
t
REF
1
5
1
5
ns
Refresh period
Notes: 1. AC measurement assumes t
T
= 1 ns. Reference level for timing of input signals is 1.5 V.
2. Access time is measured at 1.5 V. Load condition is C
L
= 50 pF.
3. t
LZ
(min) defines the time at which the outputs achieves the low impedance state.
4. t
HZ
(max) defines the time at which the outputs achieves the high impedance state.
5. t
CES
defines CKE setup time to CK rising edge except power down exit command.
—
64
—
64
ms
Test Conditions
Input and output timing reference levels: 1.5 V
Input waveform and output load: See following figures
Ambient illuminance: Under 100 lx
t
T
2.4 V
0.4 V0.8 V
2.0 V
input
t
T
DQ
CL
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PDF描述 |
|---|---|
| HB52RF1289E2 | 1 GB Registered SDRAM DIMM 128-Mword 】 72-bit, 133 MHz Memory Bus, 2-Bank Module (36 pcs of 64 M 】 4 Components) PC133 SDRAM |
| HB52RF1289E2 | 1 GB Registered SDRAM DIMM(1GB 寄存同步DRAM DIMM) |
| HB52RF329E2 | 256 MB Registered SDRAM DIMM(256 MB 寄存同步DRAM DIMM) |
| HB52RF648DC-B | 512 MB Unbuffered SDRAM S.O.DIMM 64-Mword 】 64-bit, 133/100 MHz Memory Bus, 2-Bank Module (16 pcs of 32 M 】 8 components) PC133/100 SDRAM |
| HB52RD648DC-B | 512 MB Unbuffered SDRAM S.O.DIMM 64-Mword 】 64-bit, 133/100 MHz Memory Bus, 2-Bank Module (16 pcs of 32 M 】 8 components) PC133/100 SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HB52RF1289E2U-75B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1 GB Registered SDRAM DIMM 128-Mword × 72-bit, 133 MHz Memory Bus, 2-Bank Module (36 pcs of 64 M × 4 Components) PC133 SDRAM |
| HB52RF328GB-75B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256MB Unbuffered SDRAM Micro DIMM |
| HB52RF328GB-75BL | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256MB Unbuffered SDRAM Micro DIMM |
| HB52RF328GB-B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256MB Unbuffered SDRAM Micro DIMM |
| HB52RF329E2-75F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 SDRAM Module |
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