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參數(shù)資料
| 型號： | HB52RD649DC-B |
| 廠商： | Elpida Memory, Inc. |
| 英文描述： | 512MB Unbuffered SDRAM S.O.DIMM |
| 中文描述： | 512MB的無緩沖內(nèi)存的SODIMM |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 464K |
| 代理商： | HB52RD649DC-B |
HB52RF649DC-B, HB52RD649DC-B
Data Sheet E0223H30 (Ver. 3.0)
10
Pin Capacitance (TA = 25°C, VCC = 3.3V ± 0.3V)
Parameter
Symbol
Pins
max.
Unit
Notes
Input capacitance
CIN
Address
110
pF
1, 2, 4
Input capacitance
CIN
/RE, /CE, /W,
/S0, /S1, CK0, CK1,
CKE0, CKE1
DQMB
110
pF
1, 2, 4
Input capacitance
CIN
65
pF
1, 2, 4
Input capacitance
CIN
30
pF
1, 2, 4
Input/Output capacitance
CI/O
DQ, CB
27
pF
1, 2, 3, 4
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. Measurement condition: f = 1MHz, 1.4V bias, 200mV swing.
3. DQMB = VIH to disable Data-out.
4. This parameter is sampled and not 100% tested.
AC Characteristics (TA = 0 to 65°C, VCC = 3.3V ± 0.3V, VSS = 0V)
-75
-A6
Parameter
System clock cycle time
(CL = 2)
(CL = 3)
Symbol
tCK
tCK
PC100
Symbol
Tclk
Tclk
min.
10
7.5
max.
—
—
min.
10
10
max.
—
—
Unit
ns
ns
Notes
1
CK high pulse width
tCKH
Tch
2.5
—
3
—
ns
1
CK low pulse width
Access time from CK
(CL = 2)
(CL = 3)
tCKL
tAC
tAC
Tcl
Tac
Tac
2.5
—
—
—
6
5.4
3
—
—
—
6
6
ns
ns
ns
1
1, 2
Data-out hold time
tOH
Toh
2.7
—
3
—
ns
1, 2
CK to Data-out low impedance
tLZ
2
—
2
—
ns
1, 2, 3
CK to Data-out high impedance tHZ
—
5.4
—
6
ns
1, 4
Input setup time
tAS, tCS,
1.5
—
2
—
ns
1, 5
CKE setup time for power down
exit
tCESP
Tpde
1.5
—
2
—
ns
1
Input hold time
tAH, tCH,
tDH,
tCEH
Thi
0.8
—
1
—
ns
1
Ref/Active to Ref/Active
command period
Active to Precharge command
period
Active command to column
command (same bank)
Precharge to active command
period
Write recovery or data-in to
precharge lead time
Active (a) to Active (b)
command period
Transition time (rise and fall)
tRC
Trc
67.5
—
70
—
ns
1
tRAS
Tras
45
120000
50
120000
ns
1
tRCD
Trcd
20
—
20
—
ns
1
tRP
Trp
20
—
20
—
ns
1
tDPL
Tdpl
15
—
20
—
ns
1
tRRD
Trrd
15
—
20
—
ns
1
tT
1
5
1
5
ns
Refresh period
tREF
—
64
—
64
ms
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