參數(shù)資料
型號: HB52RD649DC-A6BL
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 512MB Unbuffered SDRAM S.O.DIMM
中文描述: 64M X 72 SYNCHRONOUS DRAM MODULE, 6 ns, DMA144
封裝: ZIG ZAG DUAL TAB SOCKET TYPE, SODIMM-144
文件頁數(shù): 9/16頁
文件大?。?/td> 464K
代理商: HB52RD649DC-A6BL
HB52RF649DC-B, HB52RD649DC-B
Data Sheet E0223H30 (Ver. 3.0)
9
DC Characteristics 1 (TA = 0 to 65°C, VCC = 3.3V ± 0.3V, VSS = 0V)
Parameter
Symbol
Grade
Max.
Unit
Test conditions
Notes
Operating current
(CL = 2)
ICC1
-75
-A6
-75
-A6
1260
1125
1260
1125
mA
Burst length = 1
tRC = min.
1, 2, 3
(CL = 3)
ICC1
mA
Standby current in power down
ICC2P
54
mA
CKE0 = VIL,
tCK = 12ns
6
Standby current in power down
(input signal stable)
ICC2PS
36
mA
CKE0 = VIL, tCK =
7
Standby current in non power down
ICC2N
360
mA
CKE0, /S = VIH,
tCK = 12ns
CKE0, /S = VIH,
tCK = 12ns
CKE0, /S = VIH,
tCK = 12ns
4
Active standby current in power down
ICC3P
72
mA
1, 2, 6
Active standby current in non power
down
Burst operating current
(CL = 2)
ICC3N
540
mA
1, 2, 4
ICC4
-75
-A6
-75
-A6
1170
1170
1485
1170
2250
mA
tCK = min., BL = 4
1, 2, 5
(CL = 3)
ICC4
mA
Refresh current
ICC5
mA
tRC = min.
VIH
VCC – 0.2V
VIL
0.2V
3
Self refresh current
ICC6
54
mA
8
Self refresh current
(L-version)
Notes: 1. ICC depends on output load condition when the device is selected. ICC (max.) is specified at the output
open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CK0/CK1 operating current.
7. After power down mode, no CK0/CK1 operating current.
8. After self refresh mode set, self refresh current.
ICC6
36
mA
DC Characteristics 2 (TA = 0 to 65°C, VCC = 3.3V ± 0.3V, VSS = 0V)
Parameter
Symbol
Grade
min.
Max.
Unit
Test conditions
Notes
Input leakage current
ILI
–10
10
μA
0
Vin
VCC
0
Vout
VCC
DQ = disable
IOH = –4 mA
Output leakage current
ILO
–10
10
μA
Output high voltage
VOH
2.4
V
Output low voltage
VOL
0.4
V
IOL = 4 mA
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