
GS9092A Data Sheet
34715 - 0
February 2006
28 of 59
3.3.3 Ancillary Data Insertion Mode
The internal FIFO is in ancillary data insertion mode when the application layer sets 
the FIFO_EN and IOPROC_EN pins HIGH, and the FIFO_MODE[1:0] bits in the 
IOPROC_DISABLE register are configured to 10b.
In this mode, the FIFO is divided into two separate blocks of 1024 words each. To 
insert ancillary data into the video stream, the internal PLL must be locked to the 
input PCLK. 
Once the FIFO enters ancillary data insertion mode, there is a 2200 PCLK cycle 
(82us) initialization period before the application layer may write ancillary data into 
the FIFO. The device will set the ANC_FIFO_READY bit HIGH (bit 12 of address 
06h) once this initialization period has passed.
The following steps, which may be completed in any order, are required before 
ancillary data is inserted into the data stream:
1. Starting at the first address of the FIFO (address 02Ch), the application layer 
must program the contents of the ancillary data packets to be inserted into the 
FIFO via the host interface. A maximum of 1024 8-bit words are allowed. The 
entire packet, including the ancillary data flag (ADF), data identification (DID), 
secondary data identification (SDID) if applicable, data count (DC), and 
checksum word must be written into memory. The user may write an arbitrary 
value (FFh for example) for the checksum word, which will act as a place 
holder. The actual checksum will be calculated and inserted by the device 
prior to insertion into the data stream. The GS9092A will also generate bit 8 
and 9 for all words in the FIFO (as described in SMPTE 291M) prior to 
insertion. Note that no ancillary data can be written to the FIFO until the device 
has set the ANC_FIFO_READY bit HIGH.
2. The number of words to be inserted (i.e. the number of words written into the 
FIFO), must be programmed in the ANC_WORDS[10:0] register by the 
application layer. If the total number of words to be inserted exceeds the 
available space, the ancillary data will be inserted up to the point where the 
available space is filled.
3. The line(s) in which the packets are to be inserted must be programmed into 
the ANC_LINE_A[10:0] and/or ANC_LINE_B[10:0] registers. Up to two lines 
per frame may have ancillary data packets inserted in them. If only one line 
number register is programmed, ancillary data packets will be inserted in one 
line per frame only. The GS9092A will insert ancillary data into the designated 
line(s) during every frame.
4. The application layer must set the ANC_SAV bit of the IO_CONFIG register 
(address 05h) either HIGH or LOW. By default, the ANC_SAV bit will be LOW 
and the ancillary data will be inserted into the horizontal ancillary data space at 
the first available location after the EAV. If the ANC_SAV bit is set HIGH, the 
ancillary data is written instead immediately after the SAV on the line 
programmed. If an active video line is programmed into the 
ANC_LINE_A[10:0] or ANC_LINE_B[10:0] register, the active video data will 
be overwritten when ANC_SAV is set HIGH.