參數(shù)資料
型號: GS882V37AB
廠商: GSI TECHNOLOGY
英文描述: 256K x 36 9Mb SCD/DCD Sync Burst SRAMs
中文描述: 256K × 36 9Mb以上SCD的/雙氰胺同步突發(fā)靜態(tài)存儲器
文件頁數(shù): 4/28頁
文件大?。?/td> 637K
代理商: GS882V37AB
GS882V37AB/D-250/225/200
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 7/2004
4/28
2002, GSI Technology
GS882V37A BGA Pin Description
Symbol
A
0
, A
1
A
DQ
A
DQ
B
DQ
C
DQ
D
B
A
, B
B
, B
C
, B
D
NC
CK
BW
GW
E
1
G
ADV
ADSP, ADSC
ZZ
LBO
Type
I
I
Description
Address field LSBs and Address Counter Preset Inputs
Address Inputs
I/O
Data Input and Output pins
I
Byte Write Enable for DQ
A
, DQ
B
, DQ
C
, DQ
D
I/Os; active low (x36 Version)
No Connect
Clock Input Signal; active high
Byte Write—Writes all enabled bytes; active low
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
Output Enable; active low
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
Linear Burst Order mode; active low
I
I
I
I
I
I
I
I
I
SCD
I
Single Cycle Deselect/Dual Cycle Deselect Mode Control
PE
I
9th Bit Enable; active low (High = x16/32 Mode, Low = x18/36 Mode)
ZQ
I
FLXDrive Output Impedance Control
(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])
TMS
I
Scan Test Mode Select
TDI
I
Scan Test Data In
TDO
O
Scan Test Data Out
TCK
V
DD
V
SS
V
DDQ
I
Scan Test Clock
I
Core power supply
I
I/O and Core Ground
I
Output driver power supply
V
DDQ
/DNU
V
DDQ
or V
DD
(must be tied high)
or
Do Not Use (must be left floating)
相關(guān)PDF資料
PDF描述
GS882V37AB-200 256K x 36 9Mb SCD/DCD Sync Burst SRAMs
GS882V37AB-200I 256K x 36 9Mb SCD/DCD Sync Burst SRAMs
GS882V37BB 256K x 36 9Mb SCD/DCD Sync Burst SRAM
GS882Z18AB 9Mb Pipelined and Flow Through Synchronous NBT SRAM
GS882Z18AB-133 9Mb Pipelined and Flow Through Synchronous NBT SRAM
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