參數(shù)資料
型號(hào)： GS881E36T-11I
廠商： GSI TECHNOLOGY
元件分類： DRAM
英文描述： 512K x 18, 256K x 36 ByteSafe 8Mb Sync Burst SRAMs
中文描述： 256K X 36 CACHE SRAM, 11 ns, PQFP100
封裝： TQFP-100
文件頁(yè)數(shù)： 26/34頁(yè)
文件大小： 487K
代理商： GS881E36T-11I
Rev: 1.10 9/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
26/34
2000, Giga Semconductor, Inc.
Preliminary
GS881E18/36T-11/11.5/100/80/66
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
JTAG Tap Controller State Diagram
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when
the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices
in the scan path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE/PRELOAD instruction is loaded in the Instruc-
tion Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan
Register. Because the RAM clock is independent fromthe TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring con-
tents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm
the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data cap-
ture set-up plus hold time (tTS plus tTH ). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O
ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the
TDI and TDO pins. Because the PRELOAD portion of the command is not implemented in this device, moving the controller to the Update-
DR state with the SAMPLE / PRELOAD instruction loaded in the Instruction Register has the same effect as the Pause-DR command. This
functionality is not Standard 1149.1-compliant.
Select DR
Capture DR
0
Shift DR
Exit1 DR
Pause DR
Exit2 DR
Update DR
1
Select IR
Capture IR
0
Shift IR
Exit1 IR
Pause IR
Exit2 IR
Update IR
1
Test Logic Reset
Run Test Idle
0
1
0
1
1
0
1
1
1
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
1
1
1
1
相關(guān)PDF資料
PDF描述
GS881E36T-66 512K x 18, 256K x 36 ByteSafe 8Mb Sync Burst SRAMs
GS881E36T-66I 512K x 18, 256K x 36 ByteSafe 8Mb Sync Burst SRAMs
GS881E36T-80 512K x 18, 256K x 36 ByteSafe 8Mb Sync Burst SRAMs
GS881E36T-80I 512K x 18, 256K x 36 ByteSafe 8Mb Sync Burst SRAMs
GS881E18T-100 512K x 18, 256K x 36 ByteSafe 8Mb Sync Burst SRAMs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS881E36T-66 制造商:GSI 制造商全稱:GSI Technology 功能描述:512K x 18, 256K x 36 ByteSafe 8Mb Sync Burst SRAMs
GS881E36T-66I 制造商:GSI 制造商全稱:GSI Technology 功能描述:512K x 18, 256K x 36 ByteSafe 8Mb Sync Burst SRAMs
GS881E36T-80 制造商:GSI 制造商全稱:GSI Technology 功能描述:512K x 18, 256K x 36 ByteSafe 8Mb Sync Burst SRAMs
GS881E36T-80I 制造商:GSI 制造商全稱:GSI Technology 功能描述:512K x 18, 256K x 36 ByteSafe 8Mb Sync Burst SRAMs
GS881EV18BT-250 制造商:GSI Technology 功能描述:512K X 18 (9 MEG) SYNCH BURST , DCD, JTAG - Trays
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*