參數(shù)資料
型號： GS8644Z36E-150I
廠商： Electronic Theatre Controls, Inc.
英文描述： Header; No. of Contacts:10; Pitch Spacing:0.079"; No. of Rows:2; Gender:Male; Series:1552; Body Material:Glass Filled Polyester; Connector Retention Style:Latch/Ejector; Contact Termination:Through Hole; Housing Style:Right-Angle RoHS Compliant: Yes
中文描述： 72Mb流水線和流量，通過同步唑的SRAM
文件頁數(shù)： 28/39頁
文件大?。?/td> 1174K
代理商： GS8644Z36E-150I
Product Preview
GS8644Z18(B/E)/GS8644Z36(B/E)/GS8644Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 11/2004
28/39
2003, GSI Technology
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
ID Register Contents (per die)
Die
Revision
Code
Not Used
I/O
Configuration
GSI Technology
JEDEC Vendor
ID Code
P
Bit #
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
x72
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0 1 1 0 1 1 0 0 1
1
x36
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0 1 1 0 1 1 0 0 1
1
x32
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0 1 1 0 1 1 0 0 1
1
x18
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0 1 1 0 1 1 0 0 1
1
x16
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0 1 1 0 1 1 0 0 1
1
相關(guān)PDF資料
PDF描述
GS8644Z36E-166 Header; No. of Contacts:10; Pitch Spacing:0.079"; No. of Rows:2; Gender:Male; Series:1552; Body Material:Glass Filled Polyester; Connector Retention Style:Latch/Ejector; Contact Termination:Through Hole; Housing Style:Right-Angle RoHS Compliant: Yes
GS8644Z36E-166I Header; No. of Contacts:10; Pitch Spacing:0.079"; No. of Rows:2; Gender:Male; Series:1552; Body Material:Glass Filled Polyester; Connector Retention Style:Latch/Ejector; Contact Termination:Through Hole; Housing Style:Right-Angle RoHS Compliant: Yes
GS88018AT-133 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
GS88018AT-133I 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
GS88018AT-150 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS8644Z36E-150IV 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8644Z36E-150V 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8644Z36E-166 制造商:未知廠家 制造商全稱:未知廠家 功能描述:72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8644Z36E-166I 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 2.5V/3.3V 72MBIT 2MX36 7NS/3.5NS 165FBGA - Trays 制造商:GSI 功能描述:
GS8644Z36E-166IV 制造商:GSI Technology 功能描述:SRAM SYNC SGL 1.8V/2.5V 72MBIT 2MX36 7NS/2.9NS 165FPBGA - Trays
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