參數(shù)資料
型號： GS832418C-166I
廠商： GSI TECHNOLOGY
元件分類： DRAM
英文描述： 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
中文描述： 2M X 18 CACHE SRAM, 8.5 ns, PBGA209
封裝： 14 X 22 MM, 1 MM PITCH, BGA-209
文件頁數(shù)： 1/46頁
文件大?。?/td> 1149K
代理商： GS832418C-166I
Rev: 1.00 10/2001
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology).
1/46
2001, Giga Semiconductor, Inc.
Preliminary
GS832418(B/C)/GS832436(B/C)/GS832472(C)
2M x 18, 1M x 36, 512K x 72
36Mb S/DCD Sync Burst SRAMs
250 MHz
–
133MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
119- and 209-Pin BGA
Commercial Temp
Industrial Temp
Features
FT pin for user-configurable flow through or pipeline operation
Single/Dual Cycle Deselect selectable (x36 and x72)
Dual Cycle Deselect only (x18)
IEEE 1149.1 JTAG-compatible Boundary Scan
ZQ mode pin for user-selectable high/low output drive
2.5 V or 3.3 V +10%/–5% core power supply
2.5 V or 3.3 V I/O supply
LBO pin for Linear or Interleaved Burst mode
Internal input resistors on mode pins allow floating mode pins
Default to SCD x36/x72 Interleaved Pipeline mode
Byte Write (BW) and/or Global Write (GW) operation
Internal self-timed write cycle
Automatic power-down for portable applications
JEDEC-standard 119- and 209-bump BGA package
-250 -225 -200 -166 -150 -133 Unit
Pipeline
3-1-1-1
tCycle
4.0
4.4
Curr (x18)
Curr (x36)
Curr (x72)
660
600
Curr (x18)
Curr (x36)
Curr (x72)
640
590
Flow
Through
2-1-1-1
Curr (x18)
Curr (x36)
Curr (x72)
350
350
Curr (x18)
Curr (x36)
Curr (x72)
340
340
Functional Description
Applications
The GS832418/36/72 is a 37,748,736-bit high performance 2-die
synchronous SRAM module with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device now
finds application in synchronous SRAM applications, ranging
from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the
user via the FT mode . Holding the FT mode pin low places the
RAM in Flow Through mode, causing output data to bypass the
Data Output Register. Holding FT high places the RAM in
Pipeline mode, activating the rising-edge-triggered Data Output
Register.
SCD and DCD Pipelined Reads
The GS832436(B/C) and the GS832472(C) are SCD (Single
Cycle Deselect) and DCD (Dual Cycle Deselect) pipelined
synchronous SRAMs. The GS832418(B/C) is a DCD-only
SRAM. DCD SRAMs pipeline disable commands to the same
degree as read commands. SCD SRAMs pipeline deselect
commands one stage less than read commands. SCD RAMs begin
turning off their outputs immediately after the deselect command
has been captured in the input registers. DCD RAMs hold the
deselect command for one full cycle and then begin turning off
their outputs just after the second rising edge of clock. The user
may configure the x36 or x72 versions of this SRAM for either
mode of operation using the SCD mode input.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.
FLXDrive
The ZQ pin allows selection between high drive strength (ZQ low)
for multi-drop bus applications and normal drive strength (ZQ
floating or high) point-to-point applications. See the Output Driver
Characteristics chart for details.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High)
of the ZZ signal, or by stopping the clock (CK). Memory data is
retained during Sleep mode.
Core and Interface Voltages
The GS832418/36/72 operates on a 2.5 V or 3.3 V power supply.
All input are 3.3 V and 2.5 V compatible. Separate output power
(V
DDQ
) pins are used to decouple output noise from the internal
circuits and are 3.3 V and 2.5 V compatible.
t
KQ
2.3
2.5
3.0
5.0
305
460
540
305
460
530
3.5
6.0
265
400
460
260
390
450
3.8
6.6
245
370
430
240
360
420
4.0
7.5
215
330
380
215
330
370
ns
ns
mA
mA
mA
mA
mA
mA
3.3 V
365
560
335
510
2.5 V
360
550
330
500
t
KQ
tCycle
6.0
7.0
6.5
7.5
7.5
8.5
8.5
10
10
10
11
15
ns
ns
3.3 V
235
300
230
300
210
270
300
210
270
300
200
270
300
200
270
300
195
270
300
195
270
300
150
200
220
145
190
220
mA
mA
mA
mA
mA
mA
2.5 V
235
300
230
300
相關(guān)PDF資料
PDF描述
GS832418C-200 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
GS832418C-200I 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
GS832418C-225 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
GS832418C-225I 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
GS832418C-250 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS8324Z36B-133 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 2.5V/3.3V 36MBIT 1MX36 10NS/4NS 119FBGA - Trays
GS8324Z36B-200I 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 2.5V/3.3V 36MBIT 1MX36 7.5NS/3NS 119FBGA - Trays
GS8324Z72C200 制造商:G.S.I. 功能描述:
GS8342D06BD-350 制造商:GSI Technology 功能描述:165 FBGA - Bulk
GS8342D06BD-500 制造商:GSI Technology 功能描述:165 FBGA - Bulk
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*