參數(shù)資料
型號： GS832418C-133
廠商： GSI TECHNOLOGY
元件分類： DRAM
英文描述： 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
中文描述： 2M X 18 CACHE SRAM, 10 ns, PBGA209
封裝： 14 X 22 MM, 1 MM PITCH, BGA-209
文件頁數(shù)： 36/46頁
文件大小： 1149K
代理商： GS832418C-133
Rev: 1.00 10/2001
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
36/46
2001, Giga Semiconductor, Inc.
Preliminary
GS832418(B/C)/GS832436(B/C)/GS832472(C)
Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it
is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although
allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be
stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be
paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-
DR state then places the boundary scan register between the TDI and TDO pins.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s.
The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input
pins.
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST
command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK
when the controller is in the Update-IR state.
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected,
the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are trans-
ferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s output pins drive out the
value of the Boundary Scan Register location with which each output pin is associated.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID
register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any
time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z) and the
Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state.
RFU
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
相關PDF資料
PDF描述
GS832418C-133I 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
GS832418C-150 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
GS832418C-150I 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
GS832418C-166 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
GS832418C-166I 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
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