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| 型號： | GS8321Z36GE-250 |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | 36Mb Pipelined and Flow Through Synchronous NBT SRAMs |
| 中文描述： | 1M X 36 ZBT SRAM, 6.5 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165 |
| 文件頁數(shù)： | 19/34頁 |
| 文件大?。?/td> | 746K |
| 代理商： | GS8321Z36GE-250 |
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AC Electrical Characteristics
Parameter
Symbol
-250
-225
-200
-166
-150
-133
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Pipeline
Clock Cycle Time
tKC
4.0
—
4.4
—
5.0
—
6.0
—
6.7
—
7.5
—
ns
Clock to Output Valid
tKQ
—
2.5
—
2.7
—
3.0
—
3.4
—
3.8
—
4.0
ns
Clock to Output Invalid
tKQX
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
ns
Clock to Output in Low-Z
tLZ
1
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
ns
Setup time
tS
1.2
—
1.3
—
1.4
—
1.5
—
1.5
—
1.5
—
ns
Hold time
tH
0.2
—
0.3
—
0.4
—
0.5
—
0.5
—
0.5
—
ns
Flow
Through
Clock Cycle Time
tKC
5.5
—
6.0
—
6.5
—
7.0
—
7.5
—
8.5
—
ns
Clock to Output Valid
tKQ
—
5.5
—
6.0
—
6.5
—
7.0
—
7.5
—
8.5
ns
Clock to Output Invalid
tKQX
3.0
—
3.0
—
3.0
—
3.0
—
3.0
—
3.0
—
ns
Clock to Output in Low-Z
tLZ
1
3.0
—
3.0
—
3.0
—
3.0
—
3.0
—
3.0
—
ns
Setup time
tS
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
ns
Hold time
tH
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
ns
Clock HIGH Time
tKH
1.3
—
1.3
—
1.3
—
1.3
—
1.5
—
1.7
—
ns
Clock LOW Time
tKL
1.5
—
1.5
—
1.5
—
1.5
—
1.7
—
2
—
ns
Clock to Output in
High-Z
tHZ
1
1.5
2.5
1.5
2.7
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
ns
G to Output Valid
tOE
—
2.5
—
2.7
—
3.0
—
3.5
—
3.8
—
4.0
ns
G to output in Low-Z
tOLZ
1
0
—
0
—
0
—
0
—
0
—
0
—
ns
G to output in High-Z
tOHZ
1
—
2.5
—
2.7
—
3.0
—
3.0
—
3.0
—
3.0
ns
ZZ setup time
tZZS
2
5
—
5
—
5
—
5
—
5
—
5
—
ns
ZZ hold time
tZZH
2
1
—
1
—
1
—
1
—
1
—
1
—
ns
ZZ recovery
tZZR
20
—
20
—
20
—
20
—
20
—
20
—
ns
GS8321Z18/32/36E-250/225/200/166/150/133
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.06b 2/2006
19/34
2003, GSI Technology
Notes:
1.
2.
These parameters are sampled and are not 100% tested.
ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
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