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參數(shù)資料
| 型號： | GS832018GT-133 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | DRAM |
| 英文描述： | 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs |
| 中文描述： | 200萬× 18，100萬× 32，100萬× 36同步突發(fā)靜態(tài)存儲器分配36MB |
| 文件頁數(shù)： | 20/25頁 |
| 文件大?。?/td> | 669K |
| 代理商： | GS832018GT-133 |
GS832018/32/36T-250/225/200/166/150/133
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 10/2004
20/25
2003, GSI Technology
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after 2 cycles of wake up time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I
SB
2. The duration of
Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, I
SB
2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
tZZR
tZZH
tZZS
Hold
Setup
tKL
tKH
tKC
CK
ADSP
ADSC
ZZ
相關PDF資料 |
PDF描述 |
|---|---|
| GS832018GT-133I | 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs |
| GS832032GT-133 | 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs |
| GS832032GT-133I | Film Capacitor; Voltage Rating:400VDC; Capacitor Dielectric Material:Polyester; Capacitance:4700pF; Capacitance Tolerance:+/- 10%; Lead Pitch:7.5mm; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes; Series:184 RoHS Compliant: Yes |
| GS832032GT-150 | 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs |
| GS832032GT-150I | 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| GS832018GT-133I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs |
| GS832018GT-133IV | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V/2.5V 36MBIT 2MX18 8.5NS/4NS 100TQFP - Trays |
| GS832018GT-133V | 制造商:GSI 制造商全稱:GSI Technology 功能描述:2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs |
| GS832018GT-150 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs |
| GS832018GT-150I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs |
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