參數(shù)資料
型號: GS820H32A
廠商: GSI TECHNOLOGY
英文描述: 2Mb(64K x 32Bit) Synchronous Burst SRAM(2M位(64K x 32位)同步靜態(tài)RAM(帶2位脈沖地址計數(shù)器))
中文描述: 2MB的(64K的x 32位)同步突發(fā)靜態(tài)存儲器(200萬位(64K的× 32位)同步靜態(tài)隨機存儲器(帶2位脈沖地址計數(shù)器))
文件頁數(shù): 19/23頁
文件大?。?/td> 341K
代理商: GS820H32A
Rev: 1.04 3/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
19/23
2000, Giga Semconductor, Inc.
E
GS820H32AT/Q-150/138/133/117/100/66
Sleep Mode Timing Diagram
Application Tips
Single and Dual Cycle Deselect
SCD devices force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with the output drivers inactive) in
a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there will be no bus contention in
transitions fromreads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to
manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings) but greater care must be exercised
to avoid excessive bus contention.
CK
ADSP
ADSC
tH
tKH tKL
tKC
tS
ZZ
tZZR
tZZH
tZZS
~
~
~
~
Snooze
相關(guān)PDF資料
PDF描述
GS820H32 2Mb(64K x 32Bit) Synchronous Burst SRAM(2M位(64K x 32位)同步靜態(tài)RAM(帶2位脈沖地址計數(shù)器))
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