- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383038 > GS820E32Q-6I (Electronic Theatre Controls, Inc.) 2M Synchronous Burst SRAM PDF資料下載
參數(shù)資料
| 型號(hào)： | GS820E32Q-6I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | DRAM |
| 英文描述： | 2M Synchronous Burst SRAM |
| 中文描述： | 200萬同步突發(fā)靜態(tài)存儲(chǔ)器 |
| 文件頁數(shù)： | 8/23頁 |
| 文件大小： | 345K |
| 代理商： | GS820E32Q-6I |
Rev: 1.03 2/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
8/23
1999, Giga Semconductor, Inc.
D
GS820E32T/Q-150/138/133/117/100/66
Simplified State Diagram with G
First Write
First Read
Burst Write
Burst Read
Deselect
R
W
CR
CW
X
X
W
R
R
W
R
X
X
X
CR
R
CW
CR
CR
W
CW
W
CW
Notes:
1.
2.
The diagramshows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition fromRead cycles to Write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles.
Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAMs drivers off and for incomng data to meet
Data Input Set Up Time.
3.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS820E32T | 2M Synchronous Burst SRAM |
| GS820E32T-100 | 2M Synchronous Burst SRAM |
| GS820E32T-117 | 2M Synchronous Burst SRAM |
| GS820E32T-133 | 2M Synchronous Burst SRAM |
| GS820E32T-133I | 2M Synchronous Burst SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS820E32T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2M Synchronous Burst SRAM |
| GS820E32T-100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2M Synchronous Burst SRAM |
| GS820E32T-117 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2M Synchronous Burst SRAM |
| GS820E32T-133 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2M Synchronous Burst SRAM |
| GS820E32T-133I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2M Synchronous Burst SRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。