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參數(shù)資料
| 型號： | GS820E32Q-6I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | DRAM |
| 英文描述： | 2M Synchronous Burst SRAM |
| 中文描述： | 200萬同步突發(fā)靜態(tài)存儲器 |
| 文件頁數(shù)： | 19/23頁 |
| 文件大?。?/td> | 345K |
| 代理商： | GS820E32Q-6I |
Rev: 1.03 2/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
19/23
1999, Giga Semconductor, Inc.
D
GS820E32T/Q-150/138/133/117/100/66
Sleep Mode Timing Diagram
Application Tips
Single and Dual Cycle Deselect
SCD devices force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with the output drivers inactive) in
a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there will be no bus contention in
transitions fromreads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to
manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings) but greater care must be exercised
to avoid excessive bus contention.
CK
ADSP
ADSC
tH
tKH tKL
tKC
tS
ZZ
tZZR
tZZH
tZZS
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Snooze
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS820E32T | 2M Synchronous Burst SRAM |
| GS820E32T-100 | 2M Synchronous Burst SRAM |
| GS820E32T-117 | 2M Synchronous Burst SRAM |
| GS820E32T-133 | 2M Synchronous Burst SRAM |
| GS820E32T-133I | 2M Synchronous Burst SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS820E32T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2M Synchronous Burst SRAM |
| GS820E32T-100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2M Synchronous Burst SRAM |
| GS820E32T-117 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2M Synchronous Burst SRAM |
| GS820E32T-133 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2M Synchronous Burst SRAM |
| GS820E32T-133I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2M Synchronous Burst SRAM |
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