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參數(shù)資料
| 型號(hào)： | GS82032A |
| 廠(chǎng)商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Socket Adapter; For Use With:ATMEGA168-TQFP32, ATMEGA48-TQFP32, ATMEGA88-TQFP32, ATMEGA8L-TQFP32, ATMEGA8L(FAST)-TQFP32; Pitch Spacing:.8mm |
| 中文描述： | 200萬(wàn)同步突發(fā)靜態(tài)存儲(chǔ)器 |
| 文件頁(yè)數(shù)： | 6/23頁(yè) |
| 文件大?。?/td> | 345K |
| 代理商： | GS82032A |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)當(dāng)前第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)
Rev: 1.03 2/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
6/23
1999, Giga Semconductor, Inc.
D
GS820E32T/Q-150/138/133/117/100/66
Synchronous Truth Table
Operation
Address Used
State
Diagram
Key
5
X
X
X
R
R
W
CR
CR
CW
CW
E
1
E
2
ADSP
ADSC
ADV
W
3
DQ
4
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Note:
1.
X = Dont Care, H = High, L = Low.
2.
E = T (True) if E
2
= 1 and E
3
= 0; E = F (False) if E
2
= 0 or E
3
= 1.
3.
W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
4.
G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
None
None
None
External
External
External
Next
Next
Next
Next
Current
Current
Current
Current
H
L
L
L
L
L
X
H
X
H
X
H
X
H
X
F
F
T
T
T
X
X
X
X
X
X
X
X
X
L
H
L
H
H
H
X
H
X
H
X
H
X
L
X
L
X
L
L
H
H
H
H
H
H
H
H
X
X
X
X
X
X
L
L
L
L
H
H
H
H
X
X
X
X
F
T
F
F
T
T
F
F
T
T
High-Z
High-Z
High-Z
Q
Q
D
Q
Q
D
D
Q
Q
D
D
5.
All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See
BOLD
items above.
Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See
ITALIC
items above.
6.
7.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS820E32Q-150I | 2M Synchronous Burst SRAM |
| GS820E32Q-4 | 2M Synchronous Burst SRAM |
| GS820E32Q-4I | 2M Synchronous Burst SRAM |
| GS820E32Q-5 | 2M Synchronous Burst SRAM |
| GS820E32Q-5I | 2M Synchronous Burst SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS82032AGQ-133 | 制造商:GSI Technology 功能描述:2MB (64K X 32) SYNCH BURST SCD - Trays |
| GS82032AGQ-133I | 制造商:GSI Technology 功能描述:2MB (64K X 32) SYNCH BURST SCD - Trays |
| GS82032AGQ-150I | 制造商:GSI Technology 功能描述:2MB (64K X 32) SYNCH BURST SCD - Trays |
| GS82032AGQ-166 | 制造商:GSI Technology 功能描述:2MB (64K X 32) SYNCH BURST SCD - Trays |
| GS82032AGQ-166I | 制造商:GSI Technology 功能描述:2MB (64K X 32) SYNCH BURST SCD - Trays |
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