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參數(shù)資料
| 型號： | GS82032A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Socket Adapter; For Use With:ATMEGA168-TQFP32, ATMEGA48-TQFP32, ATMEGA88-TQFP32, ATMEGA8L-TQFP32, ATMEGA8L(FAST)-TQFP32; Pitch Spacing:.8mm |
| 中文描述： | 200萬同步突發(fā)靜態(tài)存儲器 |
| 文件頁數(shù)： | 3/23頁 |
| 文件大小： | 345K |
| 代理商： | GS82032A |
Rev: 1.03 2/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
3/23
1999, Giga Semconductor, Inc.
D
GS820E32T/Q-150/138/133/117/100/66
TQFP Pin Description
E
Pin Location
37, 36
Symbol
A
0
, A
1
Type
I
Description
Address field LSB’s and Address Counter preset Inputs
35, 34, 33, 32, 100, 99, 82, 81, 44, 45,
46, 47, 48, 49
52, 53, 56, 57, 58, 59, 62, 63
68, 69, 72, 73, 74, 75, 78, 79
2, 3, 6, 7, 8, 9, 12, 13
18, 19, 22, 23, 24, 25, 28, 29
16, 38, 39, 42, 43, 66, 50, 51, 80, 1, 30
87
93, 94
95, 96
89
88
98, 92
97
86
83
84, 85
64
14
31
15, 41, 65, 91
5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90
4, 11, 20, 27, 54, 61, 70, 77
A
2
-
15
I
Address Inputs
DQ
A1
-DQ
A8
DQ
B1
-DQ
B8
DQ
C1
-DQ
C8
DQ
D1
-DQ
D8
NC
BW
B
A
, B
B
B
C
, B
D
CK
GW
E
1
, E
3
E
2
G
ADV
ADSP, ADSC
ZZ
FT
LBO
V
DD
V
SS
V
DDQ
I/O
Data Input and Output pins.
No Connect
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Byte Write. Writes all enabled bytes. Active Low.
Byte Write Enable for DQ
A
, DQ
B
Data I/O’s. Active Low.
Byte Write Enable for DQ
C
, DQ
D
Data I/O’s. Active Low.
Clock Input Signal. Active High.
Global Write Enable. Writes all bytes. Active Low.
Chip Enable. Active Low.
Chip Enable. Active High.
Output Enable. Active Low.
Burst address counter advance enable. Active Low.
Address Strobe (Processor, Cache Controller). Active Low.
Sleep Mode control. Active High.
Flow Through or Pipeline mode. Active Low.
Linear Burst Order mode. Active Low.
Core power supply.
I/O and Core Ground.
Output driver power supply.
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