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參數(shù)資料
| 型號(hào)： | GS82032 |
| 廠商： | GSI TECHNOLOGY |
| 英文描述： | 2Mb（64K x 32Bit) Synchronous Burst SRAM(2M位（64K x 32位）同步靜態(tài)RAM（帶2位脈沖地址計(jì)數(shù)器）) |
| 中文描述： | 2MB的（64K的x 32位）同步突發(fā)靜態(tài)存儲(chǔ)器（200萬(wàn)位（64K的× 32位）同步靜態(tài)隨機(jī)存儲(chǔ)器（帶2位脈沖地址計(jì)數(shù)器）） |
| 文件頁(yè)數(shù)： | 8/23頁(yè) |
| 文件大?。?/td> | 344K |
| 代理商： | GS82032 |
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Rev: 1.03 2/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
8/23
1999, Giga Semconductor, Inc.
D
GS82032T/Q-150/138/133/117/100/66
Simplified State Diagram with G
First Write
First Read
Burst Write
Burst Read
Deselect
R
W
CR
CW
X
X
W
R
R
W
R
X
X
X
CR
R
CW
CR
CR
W
CW
W
CW
Notes:
1.
2.
The diagramshows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition fromRead cycles to Write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles.
Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAMs drivers off and for incomng data to meet
Data Input Set Up Time.
3.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS820E32A | 2Mb（64K x 32Bit) Synchronous Burst SRAM(2M位（64K x 32位）同步靜態(tài)RAM（帶2位脈沖地址計(jì)數(shù)器）) |
| GS820E32T-6I | 2M Synchronous Burst SRAM |
| GS820E32Q-100 | 2M Synchronous Burst SRAM |
| GS820E32Q-117 | 2M Synchronous Burst SRAM |
| GS820E32Q-133 | 2M Synchronous Burst SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS820322T-138 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64K x 32 2M Synchronous Burst SRAM |
| GS82032A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2M Synchronous Burst SRAM |
| GS82032AGQ-133 | 制造商:GSI Technology 功能描述:2MB (64K X 32) SYNCH BURST SCD - Trays |
| GS82032AGQ-133I | 制造商:GSI Technology 功能描述:2MB (64K X 32) SYNCH BURST SCD - Trays |
| GS82032AGQ-150I | 制造商:GSI Technology 功能描述:2MB (64K X 32) SYNCH BURST SCD - Trays |
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